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AD9511 Arkusz danych(PDF) 2 Page - Analog Devices |
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AD9511 Arkusz danych(HTML) 2 Page - Analog Devices |
2 / 60 page AD9511 Rev. A | Page 2 of 60 TABLE OF CONTENTS Specifications..................................................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 5 Clock Outputs ............................................................................... 6 Timing Characteristics ................................................................ 7 Clock Output Phase Noise .......................................................... 9 Clock Output Additive Time Jitter........................................... 12 PLL and Distribution Phase Noise and Spurious................... 14 Serial Control Port ..................................................................... 15 FUNCTION Pin ......................................................................... 15 STATUS Pin ................................................................................ 16 Power............................................................................................ 16 Timing Diagrams............................................................................ 17 Absolute Maximum Ratings.......................................................... 18 Thermal Characteristics ............................................................ 18 ESD Caution................................................................................ 18 Pin Configuration and Function Descriptions........................... 19 Terminology .................................................................................... 21 Typical Performance Characteristics ........................................... 22 Typical Modes of Operation.......................................................... 26 PLL with External VCXO/VCO Followed by Clock Distribution................................................................................. 26 Clock Distribution Only............................................................ 26 PLL with External VCO and Band-Pass Filter Followed by Clock Distribution...................................................................... 27 Functional Description .................................................................. 29 Overall.......................................................................................... 29 PLL Section ................................................................................. 29 PLL Reference Input—REFIN .............................................. 29 VCO/VCXO Clock Input—CLK2........................................ 29 PLL Reference Divider—R .................................................... 29 VCO/VCXO Feedback Divider—N (P, A, B) ..................... 29 A and B Counters................................................................... 30 Determining Values for P, A, B, and R ................................ 30 Phase Frequency Detector (PFD) and Charge Pump ....... 31 Antibacklash Pulse................................................................. 31 STATUS Pin ............................................................................ 31 PLL Digital Lock Detect........................................................ 31 PLL Analog Lock Detect ....................................................... 32 Loss of Reference.................................................................... 32 FUNCTION Pin ......................................................................... 32 RESETB: 58h<6:5> = 00b (Default)..................................... 32 SYNCB: 58h<6:5> = 01b ....................................................... 32 PDB: 58h<6:5> = 11b ............................................................ 33 Distribution Section................................................................... 33 CLK1 and CLK2 Clock Inputs.................................................. 33 Dividers........................................................................................ 33 Setting the Divide Ratio ........................................................ 33 Setting the Duty Cycle........................................................... 33 Divider Phase Offset.............................................................. 37 Delay Block ................................................................................. 38 Calculating the Delay ............................................................ 38 Outputs ........................................................................................ 38 Power-Down Modes .................................................................. 39 Chip Power-Down or Sleep Mode—PDB........................... 39 PLL Power-Down................................................................... 39 Distribution Power-Down .................................................... 39 Individual Clock Output Power-Down............................... 39 Individual Circuit Block Power-Down................................ 39 Reset Modes ................................................................................ 40 Power-On Reset—Start-Up Conditions when VS is Applied................................................................................. 40 Asynchronous Reset via the FUNCTION Pin ................... 40 Soft Reset via the Serial Port................................................. 40 |
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