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ADSP-21261SKBCZ150 Arkusz danych(PDF) 8 Page - Analog Devices |
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ADSP-21261SKBCZ150 Arkusz danych(HTML) 8 Page - Analog Devices |
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8 / 44 page  Rev. 0 | Page 8 of 44 | March 2006 ADSP-21261 DMA transfers are used to move data to and from internal memory. Access to the core is also facilitated through the paral- lel port register read/write functions. The RD, WR, and ALE (address latch enable) pins are the control pins for the parallel port. Timers The ADSP-21261 has a total of four timers: a core timer able to generate periodic software interrupts, and three general- purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes: • Pulse waveform generation mode • Pulse width count/capture mode • External event watchdog mode The core timer can be configured to use FLAG3 as a timer expired output signal, and each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A sin- gle control and status register enables or disables all three general-purpose timers independently. Program Booting The internal memory of the ADSP-21261 boots at system power-up from an 8-bit EPROM via the parallel port, an SPI master, an SPI slave, or an internal boot. Booting is determined by the boot configuration (BOOTCFG1–0) pins. Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM. Phase-Locked Loop The ADSP-21261 uses an on-chip phase-locked loop (PLL) to generate the internal clock for the core. On power-up, the CLKCFG1–0 pins are used to select ratios of 16:1, 8:1, and 3:1. After booting, numerous other ratios can be selected via soft- ware control. The ratios are made up of software configurable numerator values from 1 to 32 and software configurable divi- sor values of 1, 2, 4, 8, and 16. Power Supplies The ADSP-21261 has separate power supply connections for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.2 V requirement. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply. Note that the analog supply pin (AVDD) powers the processor’s internal clock generator PLL. To produce a stable clock, it is rec- ommended that PCB designs use an external filter circuit for the AVDD pin. Place the filter components as close as possible to the AVDD/AVSS pins. For an example circuit, see Figure 4. (A recom- mended ferrite chip is the muRata BLM18AG102SN1D). To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for VDDINT and GND. Use wide traces to connect the bypass capacitors to the analog power (AVDD) and ground (AVSS) pins. Note that the AVDD and AVSS pins specified in Figure 4 are inputs to the processor and not the analog ground plane on the board—the AVSS pin should connect directly to digital ground (GND) at the chip. TARGET BOARD JTAG EMULATOR CONNECTOR Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21261 pro- cessor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and proces- sor stacks. The processor’s JTAG interface ensures that the emulator will not affect target system loading or timing. For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appro- priate emulator hardware user’s guide. DEVELOPMENT TOOLS The ADSP-21261 is supported by a complete set of CROSSCORE ®† software and hardware development tools, including Analog Devices emulators and VisualDSP++ ®‡ development environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-21261. The VisualDSP++ project management environment lets pro- grammers develop and debug an application. This environment includes an easy to use assembler (which is based on an alge- braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The ADSP-21261 SHARC DSP has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important fea- tures. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in Figure 4. Analog Power Filter Circuit † CROSSCORE is a registered trademark of Analog Devices, Inc. ‡ VisualDSP++ is a registered trademark of Analog Devices, Inc. HI Z FERRITE BEAD CHIP LOCATE ALL COMPONENTS CLOSE TO AVDD AND AVSS PINS AVDD AVSS 100nF 10nF 1nF ADSP-21261 VDDINT |
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