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ADS8413IRGZTG4 Arkusz danych(PDF) 8 Page - Burr-Brown (TI) |
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ADS8413IRGZTG4 Arkusz danych(HTML) 8 Page - Burr-Brown (TI) |
8 / 38 page www.ti.com ADS8413 SLAS490 – OCTOBER 2005 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NO. NAME I SYNC_I + Connect to previous device SYNC_O with same polarity, while device is selected to operate in daisy Dasiy SYNC_I– chain mode. Chain 30, 31 Mode 1 (valid in cascade mode only). CLK_O available while M1=1 (LVDS) or M1+ is pulled up to M1+ I +VBD and M1– is grounded (AGND). CLK_O o/p goes to 3-state when M1 = 0 (LVDS) or M1+ is M1– Cascade grounded (AGND) and M1– is pulled up to +VBD. Do not allow these pins to float. I SDI+ Serial data input. Connect to previous device SDO with same polarity, while device is selected to Daisy SDI– operate in daisy chain mode. Chain 32, Mode 2 (valid in cascade mode only). Doubles LVDS o/p current while M2 = 1 (LVDS) or M2+ is 33 M2+ I pulled up to +VBD and M2– is grounded (AGND). LVDS o/p current is normal (3.4 mA typ) when M2 M2– Cascade = 0 (LVDS) or M2+ is grounded (AGND) and M2 – is pulled up to +VBD. Do not allow these pins to float. 34, CLK_I+ I Serial external clock input. Set CLK_I/E (pin 7) = 0 to select external clock source. 35 CLK_I– 38, CLK_O– Serial clock out. Data is latched out on the rising edge of CLK_O and can be captured on the next O 39 CLK_O+ falling edge. 40, SDO– O Serial data out. Data is latched out on the rising edge of CLK_O with MSB first format. 41 SDO+ 42, SYNC_O – O Synchronizes the data frame. (2) 43 SYNC_O + CMOS I/O PINS 1 CS I Chip select, active low signal. All of the LVDS o/p except CLK_O are 3-state if this pin is high. CMOS equivalent of CSTART input. So functionality is the same as the CSTART input. Set CONVST 2 CONVST I = 0 when the CSTART input is used. Controls the data frame(2) duration. The frame duration is 16 CLKs if BYTE = 0 or 8 CLKs if BYTE = 3 BYTE I 1. 4 PD I Active low input, acts as device power down. Selects nap mode while high. Device enters nap state at conversion end and remains so until next 5 NAP I acquisition phase begins. 6 MODE_C/D I Selects cascade (MODE_C/D = 1) or daisy chain mode (MODE_C/D = 0). Selects the source of the I/O clock. 7 CLK_I/E I CLK_I/E = 1 selects internally generated clock with 200-MHz typ frequency. CLK_I/E = 0 selects CLK_I as the I/O clock. Controls the data read with latency (LAT_Y/N = 1) or without latency ((LAT_Y/N = 0). It is essential to 8 LAT_Y/N I set LAT_Y/N = 0 for the first device in daisy chain or cascade. 46 BUSY O Active high signal, indicates a conversion is in progress. Data read request to the device, also acts as a hand shake signal for daisy chain and cascade 47 RD I operation. Status output. Indicates that the bus is being used by the device. Connect to RD of the next device 48 BUS_BUSY O for daisy chain or cascade operation. POWER SUPPLY PINS 10, 16, 21, 22, +VA – Analog power supply and LVDS input buffer power supply. 26, 37 9, 17, 20, 23, 24, AGND – Analog ground pins. Short to the analog ground plane below the device. 25, 27, 36 44 +VBD – Digital power supply for all CMOS digital inputs and CMOS, LVDS outputs. 45 BDGND – Digital ground for all digital inputs and outputs. Short to the analog ground plane below the device. (2) The duration from the first rising edge of SYNC_O to the second rising edge of SYNC_O is one data frame. The data frame duration is 16 CLKs if BYTE = 0 or 8 CLKs if BYTE = 1. 8 |
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