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ADM1175-4ARMZ-R7 Arkusz danych(PDF) 7 Page - Analog Devices

Numer części ADM1175-4ARMZ-R7
Szczegółowy opis  Hot Swap Controller and Digital Power Monitor with Convert Pin
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ADM1175-4ARMZ-R7 Arkusz danych(HTML) 7 Page - Analog Devices

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ADM1175
Rev. 0 | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC
1
SENSE
2
ON/ONB
3
GND
4
TIMER 5
GATE
10
CONV
9
ADR
8
SDA
7
SCL
6
ADM1175
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VCC
Positive Supply Input Pin. The operating supply voltage range is from 3.15 V to 16.5 V. An undervoltage
lockout (UVLO) circuit resets the ADM1175 when a low supply voltage is detected.
2
SENSE
Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin sets the analog current
limit. The hot swap operation of the ADM1175 controls the external FET gate to maintain the (VVCC − VSENSE)
voltage at 100 mV or below.
3
ON/ONB
Undervoltage or Overvoltage Input Pin. This pin is active high on the ADM1175-1 and ADM1175-2 and
active-low on the ADM1175-3 and ADM1175-4. An internal ON comparator has a trip threshold of 1.3 V,
and the output of this comparator is used as an enable for the hot swap operation. For the ON pin variants
with an external resistor divider from VCC to GND, this pin can be used to enable the hot swap operation
on a specific voltage on VCC, giving an undervoltage function. Similarly, for the ONB pin variants, an external
resistor divider can be used to create an overvoltage function, where the divider sets a voltage on VCC at
which the hot swap operation is switched off, pulling the GATE to ground.
4
GND
Chip Ground Pin.
5
TIMER
Timer Pin. An external capacitor, CTIMER, sets a 270 ms/μF initial timing cycle delay and a 21.7 ms/μF fault delay.
The GATE pin turns off when the TIMER pin is pulled beyond the upper threshold. An overvoltage detection
with an external Zener can be used to force this pin high.
6
SCL
I2C Clock Pin. Open-drain input requires an external resistive pull-up.
7
SDA
I2C Data I/O Pin. Open-drain input/output. Requires an external resistive pull-up.
8
ADR
I2C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor to set four
different I2C addresses.
9
CONV
Convert Start Pin. A high level on this pin enables an ADC conversion. The state of an internal control register,
which is set through the I2C interface, configures the part to convert current only, voltage only, or both
channels when the convert pin is asserted.
10
GATE
GATE Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the
FET drive controller, which utilizes a charge pump to provide a 12.5 μA pull-up current to charge the FET
GATE pin. The FET drive controller regulates to a maximum load current (100 mV through the sense resistor)
by modulating the GATE pin.


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