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APPLICATION INFORMATION

AUDIO SERIAL INTERFACE

L-Channel

R-Channel

LRCK

BCK

DATA

1

2

3

1

2

MSB

N–2

N

N–1

LSB

1

2

3

MSB

N–2

N

N–1

LSB

GENERAL DELAY OPERATION

TPA5052

SLOS500A – JUNE 2006 – REVISED AUGUST 2006

The audio serial interface for the TPA5052 consists of a 3-wire synchronous serial port. It includes LRCLK,

BCLK, and DATA. BCLK is the serial audio bit clock, and it is used to clock the serial data present on DATA into

the serial shift register of the audio interface. Serial data is clocked into the TPA5052 on the rising edge of

BCLK. LRCLK is the serial audio left/right word clock. It is used to latch serial data into the internal registers of

the serial audio interface. LRCLK is operated at the sampling frequency, fs. BCLK can be operated at 32 to 64

The delay of the TPA5052 is set using the 5 delay pins (DEL4, DEL3, DEL2, DEL1, DEL0). The minimum delay

is 255 samples, and occurs when all five pins are at logic 0. The maximum delay is 8191 samples, and occurs

when all five pins are at logic 1. The delay can be increased by changing the values on each pin from a 0 to a 1.

See Table 1. Delay pin DEL4 is the MSB, and DEL0 is the LSB.

The delay is calculated with the following forumula:

Audio Delay (in samples) = 4096 x (DEL4) + 2048 x (DEL3) + 1024 x (DEL2) + 512 x (DEL1) + 256 x

(DEL0) + 255

Audio Delay (ms) = Audio Delay (in samples) x (1/fs)

Both channels have the same amount of delay. They cannot be controlled individually.

Table 1. Delay Settings

DEL4

DEL3

DEL2

DEL1

DEL0

Delay in Samples

0

0

0

0

0

255

0

0

0

0

1

511

0

0

0

1

0

767

0

0

0

1

1

1023

↓

↓

↓

↓

↓

↓

1

1

1

1

1

8191

5

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