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ADUM1310BRWZ Arkusz danych(PDF) 4 Page - Analog Devices

Numer części ADUM1310BRWZ
Szczegółowy opis  Triple-Channel Digital Isolator with Programmable Default Output
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ADUM1310BRWZ Arkusz danych(HTML) 4 Page - Analog Devices

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ADuM1310
Rev. E | Page 4 of 16
ELECTRICAL CHARACTERISTICS—3 V OPERATION
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V; all voltages are relative to their respective ground.
Table 2.
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
DC SPECIFICATIONS
ADuM1310, Total Supply Current, Three Channels1
VDD1 Supply Current, Quiescent
IDD1 (Q)
1.2
1.6
mA
VIA = VIB = VIC = VID = 0
VDD2 Supply Current, Quiescent
IDD2 (Q)
0.8
1.0
mA
VIA = VIB = VIC = VID = 0
VDD1 Supply Current, 10 Mbps Data Rate
IDD1 (10)
3.4
4.9
mA
5 MHz logic signal frequency
VDD2 Supply Current, 10 Mbps Data Rate
IDD2 (10)
1.1
1.3
mA
5 MHz logic signal frequency
Input Currents
IIA, IIB, IIC, IID,
ICTRL, IDISABLE
–10
+0.01 +10
μA
0 ≤ VIA, VIB, VIC, VID, VDISABLE ≤ VDD1,
0 ≤ VCTRL ≤ VDD2
Logic High Input Threshold
VIH
1.6
V
Logic Low Input Threshold
VIL
0.4
V
Logic High Output Voltages
VOAH, VOBH,
VOCH, VODH
VDD1, VDD2 – 0.4
2.8
V
IOx = –4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL,
VOCL, VODL
0.2
0.4
V
IOx = +4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
30
50
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH – tPHL|4
PWD
5
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew (Equal Temperature)5
tPSK
30
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD
5
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High
Output7
|CMH|
25
35
kV/μs
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low
Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Input Enable Time8
tENABLE
2.0
μs
VIA, VIB, VIC, VID = 0 or VDD1
Input Disable Time8
tDISABLE
5.0
μs
VIA, VIB, VIC, VID = 0 or VDD1
Input Dynamic Supply Current per Channel9
IDDI (D)
0.10
mA/Mbps
Output Dynamic Supply Current per Channel9
IDDO (D)
0.03
mA/Mbps
1 Supply current values are for all channels combined running at identical data rates. Output supply current values are specified with no output load present. The supply
current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 4 through
Figure 6 for information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See Figure 7 through Figure 8 for total
IDD1 and IDD2 supply currents as a function of the data rate.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels within the same component.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL logic state (see Table 9).
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 4 through Figure 6 for information
on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on
calculating the per-channel supply current for a given data rate.


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