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ADSP-BF548 Arkusz danych(PDF) 6 Page - Analog Devices |
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ADSP-BF548 Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 64 page Rev. PrG | Page 6 of 82 | December 2007 ADSP-BF542/4/7/8/9 Preliminary Technical Data arranged in a hierarchical structure to provide a good cost/per- formance balance of some very fast, low-latency on-chip memory as cache or SRAM, and larger, lower-cost and perfor- mance off-chip memory systems. See Figure 3 on Page 6. The on-chip L1 memory system is the highest-performance memory available to the Blackfin processor. The off-chip mem- ory system, accessed through the external bus interface unit (EBIU), provides expansion with flash memory, SRAM, and double-rate SDRAM (DDR1), optionally accessing up to 516M bytes of physical memory. Most of the ADSP-BF542/4/7/8/9 processors also include an L2 SRAM memory array which provides up to 128K bytes of high speed SRAM operating at one half the frequency of the core, and slightly longer latency than the L1 memory banks (For informa- tion on L2 memory in each processor, see Table 1.) The L2 memory is a unified instruction and data memory and can hold any mixture of code and data required by the system design. The Blackfin cores share a dedicated low latency 64-bit wide data path port into the L2 SRAM memory. The memory DMA controllers (DMAC1 and DMAC0) pro- vides high-bandwidth data-movement capability. They can perform block transfers of code or data between the internal memory and the external memory spaces. Internal (On-Chip) Memory The ADSP-BF542/4/7/8/9 processor has several blocks of on- chip memory providing high-bandwidth access to the core. The first block is the L1 instruction memory, consisting of 48K bytes SRAM, and also 16K bytes that can be configured as a four-way set-associative cache or SRAM. This memory is accessed at full processor speed. The second on-chip memory block is the L1 data memory, con- sisting of 64K bytes SRAM, of which 32K bytes can be configured as a two-way set associative cache. This memory block is accessed at full processor speed. Figure 3. ADSP-BF547BF548/BF549 Internal/External Memory Map1 1 This memory map applies to all ADSP-BF542/4/7/8/9 processors, except for L2 memory population. ADSP-BF544 includes 64K Byte of L2 memory: 0xFEB0 0000 - 0xFEB0 FFFF. ADSP-BF542 includes no L2 memory. See also Table 1. RESERVED CORE MMR REGISTERS (2M BYTE) RESERVED SCRATCHPAD SRAM (4K BYTE) INSTRUCTION BANK B SRA M (16K BYTE) SYSTEM MMR REGISTERS (2M BYTE) RESERVED RESERVED DATA BANK B SRAM / CACHE (16K BYTE) DATA BANK B SRAM (16 K BYTE) DATA BANK A SRAM / CACHE (16K BYTE) ASYNC MEMORY BANK 3 (64M BYTE) ASYNC MEMORY BANK 2 (64M BYTE) ASYNC MEMORY BANK 1 (64M BYTE) ASYNC MEMORY BANK 0 (64M BYTE) DDR1 MEM BANK 0 (8M BYTE 256M BYTE) INSTRUCTION SRAM / CACHE (16K BYTE) 0 xFFFF FFFF 0x FEB0 0000 0 xFFB0 0000 0 xFFA2 4000 0 xFFA1 0000 0 xFF90 8000 0 xFF90 4000 0 xFF80 8000 0 xFF80 4000 0x 3000 0000 0x 2C00 0000 0x 2800 0000 0x 2400 0000 0x 2000 0000 0x EF00 0000 0x 0000 0000 0 xFFC0 0000 0 xFFB0 1000 0 xFFA0 0000 DATA BANK A SRAM (16 K BYTE) 0 xFF90 0000 0 xFF80 0000 RESERVED RESERVED 0 xFFA0 C000 0 xFFA0 8000 INSTRUCTION BANK A SRA M (32K BYTE) RESERVED B OOT ROM (4K BYTE) 0x EF00 1000 0xFFE0 0000 0x FEB2 0000 0 xFFA1 4000 L1 ROM (64K BYTE) L2 SRAM (128K BYTE) DDR1 MEM BANK 1 (8M BYTE 256M BYTE) RESERVED TOP OF LAST DDR PAGE RESERVED |
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