ADL5317

Rev. 0 | Page 9 of 16

THEORY OF OPERATION

The ADL5317 is designed to address the need for high voltage

bias control and precision optical power monitoring in optical

systems using avalanche photodiodes. It is optimized for use

with the Analog Devices, Inc. family of translinear logarithmic

amplifiers that take advantage of the wide input current range

of the ADL5317. This arrangement allows the anode of the

photodiode to connect directly to a transimpedance amplifier

for the extraction of the data stream without need for a separate

optical power monitoring tap. Figure 19 shows the basic

connections for the ADL5317.

1

FALT

2

3

4

11

IPDM

12

NC

10

NC

9

GARD

5

6

7

8

15

16

14

13

ADL5317

FALT

VSET

VPLV

VPHV

MIRROR CURRENT

OUTPUT

0.01

μF

APD

1nF

1k

Ω

0.1

μF

0.01

μF

HIGH VOLTAGE

SUPPLY

0

Ω

LOW VOLTAGE

SUPPLY

10k

Ω

0

Ω

0.01

μF

0.1

μF

Figure 19. Basic Connections

At the heart of the ADL5317 is a precision attenuating current

mirror with a voltage following characteristic that provides

precision biasing at the monitor input. This architecture uses a

JFET-input amplifier to drive the bipolar mirror and maintain

the VAPD pin. The mirror attenuates the current sourced

through VAPD by a factor of 5 to limit power dissipation under

high voltage operation and delivers the mirrored current to the

IPDM monitor output pin. Proprietary mirroring and cascoding

techniques maintain the linearity vs. the input current and

stability of the mirror ratio over a very wide range of supply and

BIAS CONTROL INTERFACE

In the linear operating mode, the voltage at VAPD is referenced

to ground, and follows the simplified equation

GARD is driven to the same potential as VAPD for use in

shielding the highly sensitive VAPD pin from leakage currents.

The GARD and VAPD pins are clamped to within approxi-

mately 40 V below the VPHV supply to prevent internal device

breakdowns, and VAPD is clamped to within a volt of GARD.

The VAPD adjustment range for a given high voltage supply,

41 V). For example, VAPD is specified from 40 V to 73.5 V for

a 75 V supply, and 6 V (the minimum allowed) to 28.5 V for a

30 V supply. When VAPD is driven to its lower clamp voltage

via the VSET pin, the mirror can continue to operate, but the

VAPD bias voltage no longer responds to incremental changes

GARD INTERFACE

The GARD pins primarily shield the VAPD trace from leakage

currents and filter noise from the bias control interface. GARD

resistor forms an RC network with an external capacitor from

GARD to ground that filters the thermal noise of the amplifier’s

feedback network and provides additional power supply

Figure 20, are necessary to ensure essential high frequency

compensation at the VAPD input pin over the full operating

range of the ADL5317.

GARD

ADL5317

X30

VAPD

20k

Ω

Figure 20. Filtering VAPD Using the GARD Interface

The cutoff frequency of the GARD interface for small signals

and noise is defined by

GRD

3dB

C

F

×

×

=

kΩ

20

2π

1

where:

superior noise performance at the lowest input current levels,

2.5 mA, resulting in a slew limited region for large signals,

followed by an RC decay for the final 700 mV. This decay

corresponds to the above single-pole equation. The pull-down

approximately 90 kΩ in parallel with 70 μA to ground.