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ADM483JR Arkusz danych(PDF) 1 Page - Analog Devices |
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ADM483JR Arkusz danych(HTML) 1 Page - Analog Devices |
1 / 16 page 5 V Low Power, Slew-Rate Limited RS-485/RS-422 Transceiver ADM483 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. FEATURES EIA RS-485/RS-422-compliant Data rates up to 250 kbps Slew-rate limited for low EMI 100 nA supply current in shutdown mode Low power consumption (120 µA) Up to 32 transceivers on one bus Outputs high-z when disabled or powered off –7 V to +12 V bus common-mode range Thermal shutdown and short-circuit protection Pin-compatible with MAX483 Specified over –40°C to +85°C temperature range Available in 8-lead SOIC package APPLICATIONS Low power RS-485 applications EMI sensitive systems DTE-DCE interfaces Industrial control Packet switching Local area networks Level translators FUNCTIONAL BLOCK DIAGRAM RO RE R DE DI D A B GND VCC ADM483 Figure 1. GENERAL DESCRIPTION The ADM483 is a low power differential line transceiver suitable for half-duplex data communication on multipoint bus trans- mission lines. It is designed for balanced data transmission, and complies with EIA Standards RS-485 and RS-422.The part contains a differential line driver and a differential line receiver. Both share the same differential pins, with either the driver or the receiver being enabled at any given time. The device has an input impedance of 12 kΩ, allowing up to 32 transceivers on one bus. Since only one driver should be enabled at any time, the output of a disabled or powered-down driver is three-stated to avoid overloading the bus. This high impedance driver output is maintained over the entire common-mode voltage range from –7 V to +12 V. The receiver contains a fail-safe feature that results in a logic high output state if the inputs are unconnected (floating). The driver outputs are slew-rate limited to reduce EMI and data errors caused by reflections from improperly terminated buses. Excessive power dissipation caused by bus contention or by output shorting is prevented by a thermal shutdown circuit. The part is fully specified over the industrial temperature range, and is available in an 8-lead SOIC package. |
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