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ADM6820ARJZ-REEL7 Arkusz danych(PDF) 7 Page - Analog Devices |
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ADM6820ARJZ-REEL7 Arkusz danych(HTML) 7 Page - Analog Devices |
7 / 12 page ADM6819/ADM6820 Rev. 0 | Page 7 of 12 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VCC1 1 GND 2 SETV 3 VCC2 6 GATE 5 EN 4 ADM6819 TOP VIEW (Not to Scale) Figure 6. ADM6819 Pin Configuration VCC1 1 GND 2 SETV 3 VCC2 6 GATE 5 SETD 4 ADM6820 TOP VIEW (Not to Scale) Figure 7. ADM6820 Pin Configuration Table 4. Pin Function Descriptions Pin Number ADM6819 ADM6820 Mnemonic Description 1 1 VCC1 Supply Voltage 1. Either VCC1 or VCC2 must be greater than the UVLO to enable external FET Drive. 2 2 GND Chip Ground Pin. 3 3 SETV Sequenced Threshold Set. Connect to an external resistor divider to set the VCC1 threshold that enables GATE turn-on. The internal reference is 0.618 V. 4 – EN Active-High Enable. GATE drive is enabled tDELAY after EN is driven high. GATE drive is immediately disabled when EN is driven low. Connect this pin to the higher of VCC1 or VCC2 if not used. EN is internally identical to SETV (0.618 V threshold) and, therefore, can be used as a second supply monitor, enabling two supplies to be validated before sequencing begins. – 4 SETD GATE Delay Set Input. Connect an external capacitor from SETD to GND to adjust the delay from SETV > VTH to GATE turn-on. tDELAY(s) = 2.652 × 106 × CSET(F). 5 5 GATE GATE Drive Output. GATE drives an external N-channel FET to connect VCC2 to the load. GATE drive enables tDELAY after SETV exceeds VTH and ENABLE is driven high. GATE drive is immediately disabled when SETV drops below VTH or ENABLE is driven low. When enabled, an internal charge pump drives GATE above VCCX to fully enhance the external N-channel FET. 6 6 VCC2 Supply Voltage 2. Either VCC1 or VCC2 must be greater than the UVLO to enable the external FET Drive. |
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