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ADSP-BF538 Arkusz danych(PDF) 3 Page - Analog Devices |
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ADSP-BF538 Arkusz danych(HTML) 3 Page - Analog Devices |
3 / 56 page ADSP-BF538/ADSP-BF538F Preliminary Technical Data Rev. PrD | Page 3 of 56 | May 2006 GENERAL DESCRIPTION The ADSP-BF538/ADSP-BF538F processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin pro- cessors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like micro- processor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction set architecture. The ADSP-BF538/ADSP-BF538F processors are completely code compatible with other Blackfin processors, differing only with respect to performance, peripherals, and on-chip memory. Specific performance, peripherals, and memory configurations are shown in Table 1. By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next generation applications that require RISC-like program- mability, multimedia support and leading edge signal processing in one integrated package. LOW POWER ARCHITECTURE Blackfin processors provide world class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature dynamic power management, the ability to vary both the voltage and fre- quency of operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This translates into longer battery life and lower heat dissipation. SYSTEM INTEGRATION The ADSP-BF538/ADSP-BF538F processors are highly inte- grated system-on-a-chip solution for the next generation of consumer and industrial applications including audio and video signal processing. By combining advanced memory configura- tions, such as on-chip flash memory, with industry-standard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The system peripherals include three UART ports, three SPI ports, four serial ports (SPORT), one CAN interface, 2 two wire interfaces (TWI), four general- purpose timers (three with PWM capability), a real-time clock, a watchdog timer, a parallel peripheral interface, general-purpose I/O, and general-purpose I/O pins. ADSP-BF538/ADSP-BF538F PROCESSOR PERIPHERALS The ADSP-BF538/ADSP-BF538F processors contain a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see the block diagram on Page 1). The general-purpose peripherals include functions such as UART, Timers with PWM (pulse width modulation) and pulse measurement capability, general-purpose I/O pins, a real time clock, and a watchdog timer. This set of functions sat- isfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the device. In addition to these general-purpose peripherals, the ADSP-BF538/ADSP-BF538F processors contain high speed serial and parallel ports for interfacing to a variety of audio, video, and modem codec functions. A CAN 2.0B controller is provided for automotive control networks. An interrupt con- troller manages interrupts from the on-chip peripherals or external sources. Power management control functions tailor the performance and power characteristics of the processors and system to many application scenarios. All of the peripherals, except for general-purpose I/O, CAN, TWI, real time clock, and timers, are supported by a flexible DMA structure. There are also two separate memory DMA con- trollers dedicated to data transfers between the processor's various memory spaces, including external SDRAM and asyn- chronous memory. Multiple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. The ADSP-BF538/ADSP-BF538F processors include an on-chip voltage regulator in support of the ADSP-BF538/ADSP-BF538F processor’s dynamic power management capability. The voltage regulator provides a range of core voltage levels from a single 2.25 V to 3.6 V input. The voltage regulator can be bypassed at the user's discretion. Table 1. Processor Features Feature Maximum Performance 500 MHz 1000 MMACs Instruction SRAM/Cache 16 K bytes Instruction SRAM 64 K bytes Data SRAM/Cache 32 K bytes Data SRAM 32 K bytes Scratchpad 4 K bytes Flash NA 512 K bytes 1 M byte SPORTs 4 SPIs 3 TWIs (connection to I 2C compatible devices) 2 UARTs 3 CAN 1 PPI 1 Package Option See Ordering Guide on Page 55 |
Podobny numer części - ADSP-BF538 |
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Podobny opis - ADSP-BF538 |
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