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ADSP-BF537 Arkusz danych(PDF) 1 Page - Analog Devices

Numer części ADSP-BF537
Szczegółowy opis  Blackfin Embedded Processor
Download  68 Pages
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Strona internetowa  http://www.analog.com
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ADSP-BF537 Arkusz danych(HTML) 1 Page - Analog Devices

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Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Blackfin®
Embedded Processor
ADSP-BF534/ADSP-BF536/ADSP-BF537
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
FEATURES
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
0.8V to 1.2V core VDD with on-chip voltage regulation
2.5 V and 3.3 V-tolerant I/O with specific 5 V-tolerant pins
182-ball and 208-ball MBGA packages
MEMORY
Up to 132K bytes of on-chip memory comprised of:
Instruction SRAM/cache; instruction SRAM;
data SRAM/cache; additional dedicated data SRAM;
scratchpad SRAM (see Table 1 on Page 3 for available
memory configurations)
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Flexible booting options from external flash, SPI and TWI
memory or from SPI, TWI, and UART host devices
Memory management unit providing memory protection
PERIPHERALS
IEEE 802.3-compliant 10/100 Ethernet MAC (ADSP-BF536 and
ADSP-BF537 only)
Controller area network (CAN) 2.0B interface
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
Two dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting eight stereo I2S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC
Two memory-to-memory DMAs with external request lines
Event handler with 32 interrupt inputs
Serial peripheral interface (SPI)-compatible
Two UARTs with IrDA® support
Two-wire interface (TWI) controller
Eight 32-bit timer/counters with PWM support
Real-time clock (RTC) and watchdog timer
32-bit core timer
48 general-purpose I/Os (GPIOs), 8 with high current drivers
On-chip PLL capable of 1
to 63
frequency multiplication
Debug/JTAG interface
Figure 1. Functional Block Diagram
ETHERNET MAC
(ADSP-BF536/
BF537 ONLY)
TIMERS 0-7
UART 0-1
PPI
SPORT1
SPI
WATCHDOG TIMER
RTC
TWI
CAN
SPORT0
GPIO
PORT
F
GPIO
PORT
H
GPIO
PORT
G
PORT
J
EXTERNAL PORT
FLASH, SDRAM CONTROL
BOOT ROM
JTAG TEST AND EMULATION
VOLTAGE REGULATOR
DMA
CONTROLLER
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
B
INTERRUPT
CONTROLLER
PERIPHERAL ACCESS BUS
EXTERNAL
ACCESS
BUS
DMA CORE BUS
16


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