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ADT7475ARQZ-REEL Arkusz danych(PDF) 11 Page - Analog Devices |
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ADT7475ARQZ-REEL Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 68 page ADT7475 Rev. A | Page 11 of 68 R/W 0 SCL SDA 10 1 1 1 0 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADT7475 STOP BY MASTER START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE 1 1 9 ACK. BY ADT7475 9 Figure 15. Writing to the Address Pointer Register Only SCL D7 R/W 0 SDA 10 1 1 1 0 START BY MASTER D6 D5 D4 D3 D2 D1 D0 NO ACK. BY MASTER STOP BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 DATA BYTE FROM ADT745 1 1 9 ACK. BY ADT7475 9 ata from a Previously S a write col. us Specifications Rev. 2.0 for more w operation. ERATIONS s specification defines several protocols for differ- read and write operations. The ones used in the cussed in this section. The following the diagrams: S—START Figure 16. Reading D elected Register It is possible to read a data byte from a data register without first writing to the address pointer register, if the address pointer register is already at the correct value. However, it is not possible to write data to a register without writing to the address pointer register, because the first data byte of is always written to the address pointer register. In addition to supporting the send byte and receive byte pro- tocols, the ADT7475 also supports the read byte proto (See System Management B information; this document is available from Intel.) If several read or write operations must be performed in succession, the master can send a repeat start condition instead of a stop condition to begin a ne WRITE OP The SMBu ent types of ADT7475 are dis abbreviations are used in P—STOP R—READ W—WRITE A—ACKNOWLEDGE A—NO ACKNOWLEDGE The ADT7475 uses the following SMBus write protocols. Send h and to condition on SDA. 3. The addressed slave device asserts ACK on SDA. 75, the send byte protocol is used to write a s to RAM for a subsequent single byte read from Byte In t is operation, the master device sends a single comm byte a slave device as follows: 1. The master device asserts a start 2. The master sends the 7-bit slave address followed by the write bit (low). 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master asserts a stop condition on SDA and the transaction ends. For the ADT74 register addres the same address. This operation is shown in Figure 17. SLAVE ADDRESS WA S A P REGISTER ADDRESS 23 1 5 4 6 Figure 17. Setting a Register Address for a Subsequent Read If the master is required to read data from the register i ert a repeat st mmedi- art d arry out a g intermediate stop d h e and one e device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master sends a data byte. 7. The slave asserts ACK on SDA. 8. The master asserts a stop condition on SDA and the transaction ends. ately after setting up the address, it can ass con ition immediately after the final ACK and c sin le byte read without asserting an con ition. Write Byte In t is operation, the master device sends a command byt data byte to the slav |
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