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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ADUC7019 Arkusz danych(PDF) 9 Page - Analog Devices |
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ADUC7019 Arkusz danych(HTML) 9 Page - Analog Devices |
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9 / 92 page  ADuC7019/20/21/22/24/25/26/27 Rev. A | Page 9 of 92 TIMING SPECIFICATIONS Table 2. External Memory Write Cycle Parameter Min Typ Max Unit CLK UCLK TMS_AFTER_CLKH 0 4 ns TADDR_AFTER_CLKH 4 8 ns TAE_H_AFTER_MS ½ CLK TAE (XMxPAR[14:12] + 1) x CLK THOLD_ADDR_AFTER_AE_L ½ CLK + (!XMxPAR[10]) x CLK THOLD_ADDR_BEFORE_WR_L (!XMxPAR[8]) x CLK TWR_L_AFTER_AE_L ½ CLK + (!XMxPAR[10] + !XMxPAR[8]) x CLK TDATA_AFTER_WR_L 8 12 ns TWR (XMxPAR[7:4] + 1) x CLK TWR_H_AFTER_CLKH 0 4 ns THOLD_DATA_AFTER_WR_H (!XMxPAR[8]) x CLK TBEN_AFTER_AE_L ½ CLK TRELEASE_MS_AFTER_WR_H (!XMxPAR[8] + 1) x CLK CLK CLK TMS_AFTER_CLKH TAE_H_AFTER_MS TAE TWR_L_AFTER_AE_L MS AE WR RD A/D[15:0] FFFF 9ABC 5678 9ABE 1234 BEN0 BEN1 A16 TWR TWR_H_AFTER_CLKH THOLD_DATA_AFTER_WR_H THOLD_ADDR_AFTER_AE_L THOLD_ADDR_BEFORE_WR_L TDATA_AFTER_WR_L TBEN_AFTER_AE_L TADDR_AFTER_CLKH TRELEASE_MS_AFTER_WR_H Figure 3. External Memory Write Cycle |
Podobny numer części - ADUC7019 |
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Podobny opis - ADUC7019 |
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