AD5532ABC-2 datasheet(4/16 Pages) AD

Numer części	AD5532ABC-2

Szczegółowy opis	32-Channel Precision Infinite Sample-and-Hold

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REV. A

–4–

AD5533B

TIMING CHARACTERISTICS

PARALLEL INTERFACE

Limit at TMIN, TMAX

Parameter

1, 2

(B Version)

Unit

Conditions/Comments

t1

0

ns min

CS to WR Setup Time

t2

0

ns min

CS to WR Hold Time

t3

50

ns min

CS Pulsewidth Low

t4

50

ns min

WR Pulsewidth Low

t5

20

ns min

A4–A0, CAL, OFFS_SEL to

WR Setup Time

t6

7

ns min

A4–A0, CAL, OFFS_SEL to

WR Hold Time

NOTES

1See Parallel Interface Timing Diagram.

2Guaranteed by design and characterization, not production tested.

Speciﬁcations subject to change without notice.

SERIAL INTERFACE

Limit at TMIN, TMAX

Parameter

1, 2

(B Version)

Unit

Conditions/Comments

fCLKIN

20

MHz max

SCLK Frequency

t1

20

ns min

SCLK High Pulsewidth

t2

20

ns min

SCLK Low Pulsewidth

t3

15

ns min

SYNC Falling Edge to SCLK Falling Edge Setup Time

t4

50

ns min

SYNC Low Time

t5

10

ns min

DIN Setup Time

t6

5

ns min

DIN Hold Time

t7

5

ns min

SYNC Falling Edge to SCLK Rising Edge Setup Time for Readback

t8

3

20

ns max

SCLK Rising Edge to DOUT Valid

t9

3

60

ns max

SCLK Falling Edge to DOUT High Impedance

t10

400

ns min10th SCLK Falling Edge to

SYNC Falling Edge for Readback

t11

4

7

ns min

SCLK Falling Edge to

SYNC Falling Edge Setup Time for

Readback

NOTES

1See Serial Interface Timing Diagrams.

2Guaranteed by design and characterization, not production tested.

3These numbers are measured with the load circuit of Figure 2.

4

SYNC should be taken low while SCLK is low for readback.

Speciﬁcations subject to change without notice.

PARALLEL INTERFACE TIMING DIAGRAM

CS

WR

A4–A0, CAL,

OFFS SEL

Figure 1. Parallel Write (ISHA Mode Only)

IOL

200 A

IOH

200 A

CL

50pF

TO

OUTPUT

1.6V

Figure 2. Load Circuit for DOUT Timing Speciﬁcations

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