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AD5602YKSZ-1REEL7 Arkusz danych(PDF) 5 Page - Analog Devices |
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AD5602YKSZ-1REEL7 Arkusz danych(HTML) 5 Page - Analog Devices |
5 / 24 page AD5602/AD5612/AD5622 Rev. B | Page 5 of 24 Limit at TMIN, TMAX Parameter Conditions2 Min Max Unit Description t8 Standard mode 4 μs tSU;STO, setup time for a stop condition Fast mode 0.6 μs High speed mode 160 ns t9 Standard mode 1000 ns tRDA, rise time of SDA signal Fast mode 300 ns High speed mode, CB = 100 pF 10 80 ns High speed mode, CB = 400 pF 20 160 ns t10 Standard mode 300 ns tFDA, fall time of SDA signal Fast mode 300 ns High speed mode, CB = 100 pF 10 80 ns High speed mode, CB = 400 pF 20 160 ns t11 Standard mode 1000 ns tRCL, rise time of SCL signal Fast mode 300 ns High speed mode, CB = 100 pF 10 40 ns High speed mode, CB = 400 pF 20 80 ns t11A Standard mode 1000 ns tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit Fast mode 300 ns High speed mode, CB = 100 pF 10 80 ns High speed mode, CB = 400 pF 20 160 ns t12 Standard mode 300 ns tFCL, fall time of SCL signal Fast mode 300 ns High speed mode, CB = 100 pF 10 40 ns High speed mode, CB = 400 pF 20 80 ns tSP4 Fast mode 0 50 ns Pulse width of spike suppressed High speed mode 0 10 ns 1 See Figure 2. High speed mode timing specification applies to the AD5602-1/AD5612-1/AD5622-1 only. Standard and fast mode timing specifications apply to the AD5602-1/AD5612-1/AD5622-1 and AD5602-2/AD5612-2/AD5622-2. 2 CB refers to the capacitance on the bus line. 3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 4 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode. TIMING DIAGRAM SCL SDA PS S P t8 t6 t5 t3 t10 t9 t4 t6 t1 t7 t2 t11 t12 Figure 2. 2-Wire Serial Interface Timing Diagram |
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Podobny opis - AD5602YKSZ-1REEL7 |
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