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AD5664RBRMZ-3REEL7 Arkusz danych(PDF) 9 Page - Analog Devices

Numer części AD5664RBRMZ-3REEL7
Szczegółowy opis  Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/C On-Chip Reference
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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AD5664RBRMZ-3REEL7 Arkusz danych(HTML) 9 Page - Analog Devices

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AD5624R/AD5644R/AD5664R
Rev. A | Page 9 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
VOUTA
10
VREFIN/VREFOUT
2
VOUTB
9
VDD
3
GND
8
DIN
4
VOUTC
7
SCLK
5
VOUTD
6
SYNC
AD5624R/
AD5644R/
AD5664R
TOP VIEW
(Not to Scale)
EXPOSED PAD TIED TO
GND ON LFCSP PACKAGE
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VOUTA
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
2
VOUTB
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
3
GND
Ground Reference Point for all Circuitry on the Part.
4
VOUTC
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
5
VOUTD
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
6
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling
edges of the next 24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an
interrupt and the write sequence is ignored by the device.
7
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 50 MHz.
8
DIN
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
9
VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
10
VREFIN/VREFOUT
The AD5624R/AD5644R/AD5664R have a common pin for reference input and reference output. When using the
internal reference, this is the reference output pin. When using an external reference, this is the reference input
pin. The default for this pin is as a reference input.


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