AD5680BRJZ-1REEL7 datasheet(11/20 Pages) AD

Numer części	AD5680BRJZ-1REEL7

Szczegółowy opis	5 V 18-Bit nanoDAC in a SOT-23

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Producent	AD [Analog Devices]

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11 / 20 page

AD5680

Rev. 0 | Page 11 of 20

THEORY OF OPERATION

DAC SECTION

The AD5680 DAC is fabricated on a CMOS process. The

architecture consists of a string DAC followed by an output

buffer amplifier. Figure 22 shows a block diagram of the DAC

architecture.

VDD

R

VOUT

GND

RESISTOR

STRING

REF (+)

REF (–)

OUTPUT

AMPLIFIER

DAC REGISTER

VFB

Figure 22. DAC Architecture

Because the input coding to the DAC is straight binary, the ideal

output voltage is given by

⎟

⎠

⎞

⎜

⎝

⎛

×

=

262144

D

V

REF

OUT

where D is the decimal equivalent of the binary code that is

loaded to the DAC register. It can range from 0 to 262143.

RESISTOR STRING

The resistor string section is shown in Figure 23. It is simply a

string of resistors, each of value R. The code loaded to the DAC

register determines at which node on the string the voltage is

tapped off to be fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the string

to the amplifier. Because it is a string of resistors, it is guaranteed

monotonic.

R

TO OUTPUT

AMPLIFIER

Figure 23. Resistor String

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages on

its output, which gives an output range of 0 V to VDD. This output

buffer amplifier has a gain of 2 derived from a 50 kΩ resistor

divider network in the feedback path. The output amplifier’s

inverting input is available to the user, allowing for remote

sensing. This VFB pin must be connected to VOUT for normal

operation. It can drive a load of 2 kΩ in parallel with 1000 pF to

GND. The source and sink capabilities of the output amplifier can

be seen in Figure 9. The slew rate is 1.5 V/μs with a ¼ to ¾ full-

scale settling time of 10 μs.

INTERPOLATOR ARCHITECTURE

The AD5680 contains a 16-bit DAC with an internal clock

generator and interpolator. The voltage levels generated by the

16-bit, 1 LSB step can be subdivided using the interpolator to

increase the resolution to 18 bits.

The 18-bit input code can be divided into two segments:

16-bit DAC code (DB19 to DB4) and 2-bit interpolator code

(DB3 and DB2). The input to the DAC is switched between a

16-bit code (for example, Code 1023) and a 16-bit code + 1 LSB

(for example, Code 1024). The 2-bit interpolator code deter-

mines the duty cycle of the switching and hence the 18-bit

code level. See Table 5 for an example.

Table 5.

18-Bit Code

16-Bit

DAC Code

2-Bit

Interpolator Code

DB19 to DB2

DB19 to DB4

DB3

DB2

Duty Cycle

4092

1023

0

4093

1023

0

1

25%

4094

1023

1

0

50%

4095

1023

1

75%

4096

1024

0

The DAC output voltage is given by the average value of

the waveform switching between 16-bit code (C) and 16-bit

code + 1 (C + 1). The output voltage is a function of the duty

cycle of the switching.

C

2

16

18

+1

C

PLANT

DAC

VOUT

FILTER

18-BIT INPUT CODE

MUX

C + 1

CLK

INTERPOLATOR

75% DUTY CYCLE

50% DUTY CYCLE

25% DUTY CYCLE

C + 1

Figure 24. Interpolation Architecture

Podobny numer części - AD5680BRJZ-1REEL7

Producent	Numer części	Arkusz danych	Szczegółowy opis
Analog Devices	AD5680BRJZ-1REEL7	451Kb / 20P	5V 18-Bit nanoDAC

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Podobny opis - AD5680BRJZ-1REEL7

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Analog Devices	AD5680	460Kb / 20P	5 V 18-Bit nanoDAC in a SOT-23 REV. B
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	AD5620	558Kb / 24P	Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23 REV. A
	AD5660	661Kb / 28P	Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23 Rev. G
	AD5062	464Kb / 20P	Fully Accurate 16-Bit VOUT nanoDAC SPI Interface 2.7 V to 5.5 V, in an SOT-23 REV. A

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