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ADUM5241BRZ Arkusz danych(PDF) 3 Page - Analog Devices

Numer części ADUM5241BRZ
Szczegółowy opis  Dual-Channel Isolators with Integrated DC/DC Converter, 50 mW
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ADUM5241BRZ Arkusz danych(HTML) 3 Page - Analog Devices

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Preliminary Technical Data
ADuM5240/ADuM5241/ADuM5242
Rev. PrN | Page 3 of 10
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
AC SPECIFICATIONS
Minimum Pulse Width5
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate6
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay7
tPHL, tPLH
25
70
ns
CL = 15 pF, CMOS signal levels
Pulse-Width Distortion, |tPLH − tPHL|7
PWD
3
ns
CL = 15 pF, CMOS signal levels
Propagation Delay Skew8
tPSK
45
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels9
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels10
tPSKCD
15
ns
CL = 15 pF, CMOS signal levels
Ripple11
200
mVP-P
Enable Time12
TENABLE
50
ns
Disable Time12
TDISABLE
50
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic High Output
|CMH|
25
35
kV/μs
VIx = VDD, VISO, VCM = 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output
|CML|
25
35
kV/μs
VIx = 0 V, V = 1000 V,
transient magnitude = 800 V
Refresh Frequency
fr
1.0
MHz
1 All voltages are relative to their respective ground.
2 Supply current values are specified with no load present on the digital outputs.
3 Supply current values are specified with no load present on the digital outputs.
4 Enable/disable threshold is the voltage at which the internal DC/DC converter is enabled/disabled.
5 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
6 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
7 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
8 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
9 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads.
10 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads.
11 Ripple occurs at frequency corresponding to the input signal data rate or the refresh frequency for data rates below 1Mbps.
12 Enable time is the duration from when input supply voltage rises above the enable threshold to when the internal DC/DC converter starts charging an external load.
Disable time is the duration from when the input supply voltage drops below the disable threshold to when the internal DC/DC converter stops charging an external
load
PACKAGE CHARACTERISTICS
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Resistance (Input-Output)
RI-O
1012
Ω
Capacitance (Input-Output)
CI-O
1.0
pF
f = 1 MHz
Input Capacitance
CI
4.0
pF
IC Junction-to-Air Thermal Resistance
θJA
150
°C/W


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