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AD9233-80EB Arkusz danych(PDF) 9 Page - Analog Devices

Numer części AD9233-80EB
Szczegółowy opis  12-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

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AD9233
Rev. A | Page 9 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
(LSB) D0
D1
D2
D3
D4
D5
DRGND
DRVDD
D6
D7
D8
D9
RBIAS
CML
AVDD
AGND
VIN–
VIN+
AGND
REFT
REFB
VREF
SENSE
35
PDWN
36
34
33
32
31
30
29
28
27
26
25
AD9233
TOP VIEW
(Not to Scale)
PIN 0 (EXPOSED PADDLE): AGND
NC = NO CONNECT
PIN 1
INDICATOR
Figure 3. Pin Configuration
Table 7. Pin Function Description
Pin No.
Mnemonic
Description
0, 21, 23, 29,
32, 37, 41
AGND
Analog Ground. (Pin 0 is the exposed thermal pad on the bottom of the package.)
1 to 6, 9 to 14
D0 (LSB) to D11 (MSB)
Data Output Bits.
7, 16, 47
DRGND
Digital Output Ground.
8, 17, 48
DRVDD
Digital Output Driver Supply (1.8 V to 3.3 V).
15
OR
Out-of-Range Indicator.
18
SDIO/DCS
Serial Port Interface (SPI)® Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select
(External Pin Mode). See Table 10.
19
SCLK/DFS
SPI Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). See Table 10.
20
CSB
SPI Chip Select (Active Low).
22, 24, 33, 40, 42
AVDD
Analog Power Supply.
25
SENSE
Reference Mode Selection. See Table 9.
26
VREF
Voltage Reference Input/Output.
27
REFB
Differential Reference (−).
28
REFT
Differential Reference (+).
30
VIN+
Analog Input Pin (+).
31
VIN–
Analog Input Pin (−).
34
CML
Common-Mode Level Bias Output.
35
RBIAS
External Bias Resister Connection. A 10 kΩ resister must be connected between this pin and
analog ground (AGND).
36
PDWN
Power-Down Function Select.
38
CLK+
Clock Input (+).
39
CLK–
Clock Input (−).
43
OEB
Output Enable (Active Low).
44
DCO
Data Clock Output.
45, 46
NC
No Connection.


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