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AD9515BCPZ-REEL7 Arkusz danych(PDF) 2 Page - Analog Devices |
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AD9515BCPZ-REEL7 Arkusz danych(HTML) 2 Page - Analog Devices |
2 / 28 page AD9515 Rev. 0 | Page 2 of 28 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Clock Input.................................................................................... 3 Clock Outputs ............................................................................... 3 Timing Characteristics ................................................................ 4 Clock Output Phase Noise .......................................................... 5 Clock Output Additive Time Jitter............................................. 8 SYNCB, VREF, and Setup Pins ................................................... 9 Power............................................................................................ 10 Timing Diagrams............................................................................ 11 Absolute Maximum Ratings.......................................................... 12 Thermal Characteristics ............................................................ 12 ESD Caution................................................................................ 12 Pin Configuration and Function Descriptions........................... 13 Terminology .................................................................................... 14 Typical Performance Characteristics ........................................... 15 Functional Description .................................................................. 18 Overall.......................................................................................... 18 CLK, CLKB—Differential Clock Input ................................... 18 Synchronization.......................................................................... 18 RSET Resistor ................................................................................ 19 VREF............................................................................................ 19 Setup Configuration................................................................... 19 Programming .................................................................................. 20 Divider Phase Offset .................................................................. 22 Delay Block ................................................................................. 22 Outputs ........................................................................................ 23 Power Supply............................................................................... 23 Power Management ................................................................... 24 Applications..................................................................................... 25 Using the AD9515 Outputs for ADC Clock Applications.... 25 LVPECL Clock Distribution ..................................................... 25 LVDS Clock Distribution .......................................................... 26 CMOS Clock Distribution ........................................................ 26 Setup Pins (S0 to S10)................................................................ 26 Power and Grounding Considerations and Power Supply Rejection...................................................................................... 26 Phase Noise and Jitter Measurement Setups........................... 27 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28 REVISION HISTORY 7/05—Revision 0: Initial Version |
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