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AD9707BCPZ Arkusz danych(PDF) 9 Page - Analog Devices |
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AD9707BCPZ Arkusz danych(HTML) 9 Page - Analog Devices |
9 / 52 page AD9704/AD9705/AD9706/AD9707 Rev. 0 | Page 9 of 52 DIGITAL SPECIFICATIONS (1.8 V) TMIN to TMAX, AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, IOUTFS = 1 mA, unless otherwise noted. Table 6. AD9707 AD9706 AD9705 AD9704 Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit DIGITAL INPUTS1 Logic 1 Voltage 1.2 1.8 1.2 1.8 1.2 1.8 1.2 1.8 V Logic 0 Voltage 0 0.5 0 0.5 0 0.5 0 0.5 V Logic 1 Current − 10 +10 − 10 +10 − 10 +10 − 10 +10 μA Logic 0 Current +10 +10 +10 +10 μA Input Capacitance 5 5 5 5 pF Input Setup Time (tS) 2.4 2.4 2.4 2.4 ns Input Hold Time (tH) 0.4 0.4 0.4 0.4 ns Latch Pulsewidth (tLPW) 6.2 6.2 6.2 6.2 ns CLK INPUTS2 Input Voltage Range 0 1.8 0 1.8 0 1.8 0 1.8 V Common-Mode Voltage 0.4 0.9 1.3 0.4 0.9 1.3 0.4 0.9 1.3 0.4 0.9 1.3 V Differential Voltage 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 V 1 Includes CLK+ pin in single-ended clock input mode. 2 Applicable to CLK+ input and CLK– input when configured for differential clock input mode. TIMING DIAGRAM DBO TO DB13 CLOCK IOUTA OR IOUTB 0.1% 0.1% tLPW tST tPD tH tS Figure 2. Timing Diagram |
Podobny numer części - AD9707BCPZ |
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Podobny opis - AD9707BCPZ |
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