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AD9942BBCZRL Arkusz danych(PDF) 7 Page - Analog Devices |
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AD9942BBCZRL Arkusz danych(HTML) 7 Page - Analog Devices |
7 / 36 page AD9942 Rev. A | Page 7 of 36 TIMING SPECIFICATIONS CL = 20 pF, fCLI = 40 MHz, serial timing in Figure 14 and Figure 15, unless otherwise noted. X = A, B. Table 5. Parameter Symbol Min Typ Max Unit MASTER CLOCK (CLI_X) (See Figure 16) CLI_X Clock Period 25.0 ns CLI_X High/Low Pulse Width tADC 10.0 12.5 15.0 ns Delay from CLI_X to Internal Pixel Period Position (See Figure 16) tCLIDLY 6 ns CLPOB_X PULSE WIDTH (Programmable)1 tCOB 2 20 Pixels SAMPLE CLOCKS (See Figure 17) SHP_X Rising Edge to SHD_X Rising Edge tS1 11.2 12.5 ns DATA OUTPUTS (See Figure 19 and Figure 20) Output Delay from Programmed Edge tOD 6 ns Pipeline Delay 11 Cycles SERIAL INTERFACE Maximum SCK_X Frequency fSCLK 10 MHz SL_X to SCK_X Setup Time tLS 10 ns SCK to SL_X Hold Time tLH 10 ns SDATA_X Valid to SCK_X Rising Edge Setup tDS 10 ns SCK_X Falling Edge to SDATA_X Valid Hold tDH 10 ns SCK_X Falling Edge to SDATA_X Valid Read tDV 10 ns 1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference. |
Podobny numer części - AD9942BBCZRL |
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Podobny opis - AD9942BBCZRL |
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