REV. 0

AD73411

–7–

PBGA BALL FUNCTION DESCRIPTIONS

BGA

Mnemonic

Location

Function

VINP

T1

This pin allows direct access to the positive input of the sigma-delta modulator.

VINN

T3

This pin allows direct access to the negative input of the sigma-delta modulator.

REFOUT

R7

Buffered Reference Output, which has a nominal value of 1.2 V.

REFCAP

R6

A Bypass Capacitor to AGND of 0.1

µF is required for the on-chip reference. The capacitor should be

fixed to this pin.

DGND

P4

AFE Digital Ground/Substrate Connection.

DVDD

P3

AFE Digital Power Supply Connection.

ARESET

P5

Active Low Reset Signal. This input resets the entire analog front end, resetting the control registers and

clearing the digital circuitry.

SCLK2

P6

Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock data

or control information to and from the serial port (SPORT2). The freque ncy of SCLK is equal to the

frequency of the master clock (AMCLK) divided by an integer number—this integer number being the product

of the external master clock rate divider and the serial clock rate divider.

AMCLK

P7

AFE Master Clock Input. AMCLK is driven from an external clock signal. If it is required to run the DSP

and AFE sections from a common clock crystal, AMCLK should be connected to the XTAL pin of the

DSP section.

SDO

R1

Serial Data Output of the Codec. Both data and control information may be output on this pin and is clocked on

the positive edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is low.

SDOFS

R2

Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and is active one SCLK

period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK.

SDOFS is in three-state when SE is low.

SDIFS

R3

Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one SCLK

period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and

is ignored when SE is low.

SDI

R4

Serial Data Input of the Codec. Both data and control information may be input on this pin and are clocked

on the negative edge of SCLK. SDI is ignored when SE is low.

SE

R5

SPORT2 Enable. Asynchronous input enable pin for SPORT2. When SE is set low by the DSP, the output

pins of SPORT2 are three-stated and the input pins are ignored. SCLK2 is also disabled internally in order

to decrease power dissipation. When SE is brought high, the control and data registers of SPORT2 are at

their original values (before SE was brought low), however the timing counte rs and other internal regis-

ters are at their reset values.

AGND

U1

AFE Analog Ground/Substrate Connection.

AVDD

U2

AFE Analog Power Supply Connection.

VOUTP

U5

Analog Output from the Positive Terminal of the Output.

VOUTN

U6

Analog Output from the Negative Terminal of the Output.

RESET

H3

(Input) Processor Reset Input.

BR

N1

(Input) Bus Request Input.

BG

L1

(Output) Bus Grant Output.

BGH

F5

(Output) Bus Grant Hung Output.

DMS

A2

(Output) Data Memory Select Output.

PMS

B2

(Output) Program Memory Select Output.

IOMS

C2

(Output) Memory Select Output.

BMS

D3

(Output) Byte Memory Select Output.

CMS

D2

(Output) Combined Memory Select Output.

RD

C3

(Output) Memory Read Enable Output.

WR

B3

(Output) Memory Write Enable Output.

IRQ2/

(Input) Edge- or Level-Sensitive Interrupt Request

PF7

D1

(Input/Output) Programmable I/O Pin.

IRQL1/

(Input) Level-Sensitive Interrupt Requests

PF6

C1

(Input/Output) Programmable I/O Pin.