Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

SN74GTLP2034GQLR Arkusz danych(PDF) 7 Page - Texas Instruments

Numer części SN74GTLP2034GQLR
Szczegółowy opis  8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
Download  21 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  TI [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI - Texas Instruments

SN74GTLP2034GQLR Arkusz danych(HTML) 7 Page - Texas Instruments

Back Button SN74GTLP2034GQLR Datasheet HTML 3Page - Texas Instruments SN74GTLP2034GQLR Datasheet HTML 4Page - Texas Instruments SN74GTLP2034GQLR Datasheet HTML 5Page - Texas Instruments SN74GTLP2034GQLR Datasheet HTML 6Page - Texas Instruments SN74GTLP2034GQLR Datasheet HTML 7Page - Texas Instruments SN74GTLP2034GQLR Datasheet HTML 8Page - Texas Instruments SN74GTLP2034GQLR Datasheet HTML 9Page - Texas Instruments SN74GTLP2034GQLR Datasheet HTML 10Page - Texas Instruments SN74GTLP2034GQLR Datasheet HTML 11Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 21 page
background image
SN74GTLP2034
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC and BIAS VCC
–0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1): AI port, ERC, and control inputs
–0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . .
B port and VREF
–0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1): AO port
–0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port
–0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: AO port
48 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any A-port output in the high state, IO (see Note 2)
48 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND
±100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0)
–50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0)
–50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
θJA (see Note 3): DGG package
70
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
58
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GQL package
42
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg
–65
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.


Podobny numer części - SN74GTLP2034GQLR

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Texas Instruments
SN74GTLP2033 TI-SN74GTLP2033 Datasheet
367Kb / 15P
[Old version datasheet]   8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SN74GTLP2033DGGR TI-SN74GTLP2033DGGR Datasheet
367Kb / 15P
[Old version datasheet]   8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SN74GTLP2033DGVR TI-SN74GTLP2033DGVR Datasheet
367Kb / 15P
[Old version datasheet]   8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SN74GTLP2033GQLR TI-SN74GTLP2033GQLR Datasheet
367Kb / 15P
[Old version datasheet]   8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
More results

Podobny opis - SN74GTLP2034GQLR

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Texas Instruments
SN74GTLP22033 TI1-SN74GTLP22033 Datasheet
645Kb / 21P
[Old version datasheet]   8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SN74GTLP22034 TI-SN74GTLP22034 Datasheet
366Kb / 20P
[Old version datasheet]   8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SN74GTLP2033 TI-SN74GTLP2033 Datasheet
367Kb / 15P
[Old version datasheet]   8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
logo
Fairchild Semiconductor
GTLP10B320 FAIRCHILD-GTLP10B320 Datasheet
261Kb / 12P
   10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
logo
Texas Instruments
SN74GTLP1394 TI1-SN74GTLP1394_15 Datasheet
890Kb / 23P
[Old version datasheet]   2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SN74GTLP1394 TI-SN74GTLP1394_07 Datasheet
741Kb / 25P
[Old version datasheet]   2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SN74GTLP21395 TI-SN74GTLP21395 Datasheet
438Kb / 21P
[Old version datasheet]   TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SN74GTLP1395 TI-SN74GTLP1395 Datasheet
443Kb / 21P
[Old version datasheet]   TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
logo
Fairchild Semiconductor
GTLP1B151 FAIRCHILD-GTLP1B151 Datasheet
112Kb / 7P
   1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path
logo
Texas Instruments
SN74GTLPH1645 TI1-SN74GTLPH1645_15 Datasheet
1Mb / 22P
[Old version datasheet]   16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21


Arkusz danych Pobierz

Go To PDF Page


Link URL




Polityka prywatności
ALLDATASHEET.PL
Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com