Triscend A7S Configurable System-on-Chip Platform
SUBJECT TO CHANGE
2
TCH305-0001-002
! Rich set of embedded support peripherals
• 4-channel high-performance DMA controller
–
fly-by performance
–
memory-to-memory transfers
–
linked-list DMA
–
frame transfer support
• Memory Subsystem Interface Unit (MSSIU)
for flexible, glueless interface to external
memories (ROM, EEPROM, Flash, SRAM,
and SDRAM)
• Two 16C550-style serial ports (UART) with
modem interface
• Two 16-bit timers/counters
• 32-bit Watchdog timer
• 16-input interrupt controller with fast
interrupt response
• IEEE 1149.1 enhanced JTAG interface
• In-system debug/breakpoint unit
• Power-on reset
• Power-down and power-management
modes
! Full-Featured Memory Interface Unit
• Simultaneous support for independent
external Flash and SDRAM memory sub-
systems using x8 or x16 memory devices
• Expandable external data bus: 8-bit, 16-bit
and 32-bit support
• Up to two external SDRAM banks
• Automatic support for self-refresh, auto-
refresh and initialization of SDRAM
• Programmable SDRAM parameters for
optimal memory bandwidth
! Embedded SRAM-based Configurable Sys-
tem Logic (CSL) matrix
• Next-generation embedded programmable
logic architecture, optimized with processor
and bus interface
• Over 2,600 flip-flops and 190 programma-
ble inputs and outputs (PIOs)
• Abundant, flexible interconnect structure
with easy access to and from system bus
• Dedicated circuitry for fast adders,
counters, and multipliers
• CSL cells optionally used as distributed
memory, including true dual-port operation
• Six independent low-skew clock or global
signal distribution buffers plus bus clock
• Supported by standard logic design tools
–
VHDL and Verilog logic synthesis
–
Schematic entry
–
VHDL and Verilog simulation
! High performance dedicated system bus
• Configurable System Interconnect (CSI)
bus integrates CSL matrix, CSoC system
• 455Mbytes per second peak transfer rate
• 32-bit address bus and 32-bit data bus
• Programmable wait-state support
• Openly-defined CSI Socket bus interface to
CSL matrix
–
CSL peripheral addresses independent
of placement in CSL matrix
–
CSL peripherals compatible with past
and future CSoC families
• Ten bus masters and built-in arbitration
–
ARM7TDMI™ CPU
–
Four-channel DMA controller
– JTAG interface
Table 1. Triscend A7S Configurable System-on-Chip Family
Device
Embedded
Processor
Core
Dedicated
Resources
System
RAM
Configurable
System Logic
(CSL) Cells
CSI
Address
Selectors
PIO*
Pins
(Max)
TA7S04
448
32
124
TA7S20
ARM7TDMI
32-bit RISC CPU
8K unified cache
Barrel shifter
Hardware multiplier
Thumb extensions
Debug extensions
Flash memory interface
SDRAM memory interface
4-channel DMA controller
Two 16C550-style UARTs
Two 16-bit timers
32-bit watchdog timer
16-input interrupt controller
Power management
Power-on reset
Hardware breakpoint unit
JTAG debugger
4Kx32
2,048
128
252
* Maximum PIO on each base device, actual PIO count depends on package style and initialization mode. See Table 61.