CDBS61880 datasheet(5/22 Pages) CIRRUS

Numer części	CDBS61880

Szczegółowy opis	Octal E1 Line Interface Evaluation Board

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Producent	CIRRUS [Cirrus Logic]

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CDB61880

DS450DB1

5

2. BOARD COMPONENT DESCRIPTIONS

2.1 Power Connections

Power for the CDB61880 evaluation board is sup-

plied by an external +3.3 V DC power supply. A +5

V DC power supply can also be connected to the

on-board control logic. The LED labeled “D3” will

illuminate when power is supplied to the on-board

control logic.

- Connect the +3.3 VDC power supply to the +3

V binding post and the +5 VDC power supply to

the +5 V binding post if 5 Volt logic is required

- Jumper J13 shown in Figure 2 allows all the

external logic on the evaluation board to be

connected to either +3 V or +5 V binding post.

- To measure the current consumption of only

the CS61880 device, place a short block on

Jumper J13 to connect the Vlogic power

supplies to the +5 V binding post. This will

isolate the CS61880 device from all the on-

board logic, to allow the current measurement

to be made at the +3 V binding post.

2.2 Master Clock Selection

In both Hardware and Host modes, the MCLK pin

is configured by placing a short block on one of the

positions of bed stake header J1. Figure 3 shows

the different positions of the J1 bed stake header.

- A 2.048 MHz clock oscillator is provided on the

evaluation board for use as the on-board clock

source for all E1 modes.

- A BNC connector (labeled J16) provides the

connection for an external clock source.

J1 3

3 V

5 V

O n -board logic c onn ec te d

to + 3 V binding pos t

O n -board logic c onn ec te d

to + 5 V binding pos t

V L OGIC

J1 3

3 V

5 V

V L OGIC

Figure 2. On-board Logic Power Selection

MCLK

J1

Data Recovery Mode

MCLK

J1

External Clock Source

J1

Receivers Powered Down

J1

On-board Oscillator

MCLK

Figure 3. Master Clock Selections

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