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DIGITAL CHARACTERISTICS

(1)

TIMING CHARACTERISTICS – LVDS AND CMOS MODES

(1)

ADS5527

SLWS196 – DECEMBER 2006

The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1 AVDD = DRVDD = 3.3 V, I

(2)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS

High-level input voltage

2.4

V

Low-level input voltage

0.8

V

High-level input current

33

µA

Low-level input current

–33

µA

Input capacitance

4

pF

DIGITAL OUTPUTS – CMOS MODE

High-level output voltage

3.3

V

Low-level output voltage

0

V

Output capacitance

Output capacitance inside the device, from each output to

2

pF

ground

DIGITAL OUTPUTS – LVDS MODE

High-level output voltage

1375

mV

Low-level output voltage

1025

mV

225

350

425

mV

Common-mode voltage of OUTP and OUTM

1200

mV

Output capacitance inside the device, from either output to

Output capacitance

2

pF

ground

(1)

All LVDS and CMOS specifications are characterized, but not tested at production.

(2)

Typical values are at 25

°C, min and max values are across the full temperature range T

DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 V

R

For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data

sheet.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperture delay

1.2

ns

Aperture jitter

150

fs rms

Time to valid data after coming out of

100

STANDBY mode

Wake-up time

µs

Time to valid data after stopping and

100

restarting the input clock

clock

Latency

14

cycles

1.0

1.5

ns

Zero-cross of CLKOUTP to data becoming

0.35

0.8

ns

(1)

Timing parameters are specified by design and characterization and not tested in production.

(2)

(3)

(4)

Measurements are done with a transmission line of 100

Ω characteristic impedance between the device and the load.

(5)

Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume

that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear

as reduced timing margin.

(6)

Data valid refers to logic high of +50 mV and logic low of –50 mV.

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