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MC14042BCL Arkusz danych(PDF) 1 Page - Motorola, Inc |
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MC14042BCL Arkusz danych(HTML) 1 Page - Motorola, Inc |
1 / 6 page MOTOROLA CMOS LOGIC DATA MC14042B 156 Quad Transparent Latch The MC14042B Quad Transparent Latch is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input. Information present at the data input is transferred to outputs Q and Q during the clock level which is determined by the polarity input. When the polarity input is in the logic “0” state, data is transferred during the low clock level, and when the polarity input is in the logic “1” state the transfer occurs during the high clock level. • Buffered Data Inputs • Common Clock • Clock Polarity Control • Q and Q Outputs • Double Diode Input Protection • Supply Voltage Range = 3.0 Vdc to 1 8 Vdc • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V lin, lout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature (8–Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/ _C From 100_C To 125_C LOGIC DIAGRAM CLOCK POLARITY VDD = PIN 16 VSS = PIN 8 5 6 4 7 13 14 D3 D2 D1 D0 LATCH 1 LATCH 2 LATCH 3 LATCH 4 Q2 Q3 Q3 Q2 Q1 Q1 Q0 Q0 12 2 3 10 9 11 1 15 MOTOROLA SEMICONDUCTOR TECHNICAL DATA © Motorola, Inc. 1995 REV 3 1/94 MC14042B L SUFFIX CERAMIC CASE 620 ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD SOIC TA = – 55° to 125°C for all packages. P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B PIN ASSIGNMENT TRUTH TABLE 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 Q2 D2 D3 Q3 VDD Q1 Q1 Q2 D0 Q0 Q0 Q3 VSS D1 POLARITY CLOCK Clock Polarity Q 0 0 Data 1 0 Latch 1 1 Data 0 1 Latch |
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