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ST7FL19F1MATRE Arkusz danych(PDF) 9 Page - STMicroelectronics |
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ST7FL19F1MATRE Arkusz danych(HTML) 9 Page - STMicroelectronics |
9 / 138 page ST7L15, ST7L19 9/138 Legend: x = undefined, R/W = read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 3. For a description of the Debug Module registers, see ST7 ICC Protocol Reference Manual. 0031h 0032h 0033h SPI SPIDR SPICR SPICSR SPI Data I/O Register SPI Control Register SPI Control Status Register xxh 0xh 00h R/W R/W R/W 0034h 0035h 0036h ADC ADCCSR ADCDRH ADCDRL A/D Control Status Register A/D Data Register High Data Low Register 00h xxh 0xh R/W Read Only R/W 0037h ITC EICR External Interrupt Control Register 00h R/W 0038h MCC MCCSR Main Clock Control/Status Register 00h R/W 0039h 003Ah Clock and Reset RCCR SICSR RC oscillator Control Register System Integrity Control/Status Register FFh 0110 0xx0b R/W R/W 003Bh PLL clock select PLLTST PLL test register 00h R/W 003Ch ITC EISR External Interrupt Selection Register 0Ch R/W 003Dh to 0048h Reserved area (12 bytes) 0049h 004Ah AWU AWUPR AWUCSR AWU Prescaler Register AWU Control/Status Register FFh 00h R/W R/W 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h DM3) DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L DMCR2 DM Control Register DM Status Register DM Breakpoint Register 1 High DM Breakpoint Register 1 Low DM Breakpoint Register 2 High DM Breakpoint Register 2 Low DM Control Register 2 00h 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W R/W 0052h to 007Fh Reserved area (46 bytes) Address Block Register Label Register Name Reset Status Remarks 1 |
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