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SN74GTL2007PWRE4 Arkusz danych(PDF) 2 Page - Texas Instruments |
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SN74GTL2007PWRE4 Arkusz danych(HTML) 2 Page - Texas Instruments |
2 / 10 page SN74GTL2007 12BIT GTL/GTL/GTL+ TO LVTTL TRANSLATOR SCLS609 − MARCH 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Function Tables INPUTS OUTPUT EN1 1BI/2BI OUTPUT 1AO/2AO H L L H HH L X H INPUTS OUTPUT EN2 3BI/4BI OUTPUT 3AO/4AO H L L H HH L X H INPUT 9BI OUTPUT 9AO L L H H INPUTS OUTPUT 10BO1/10BO2 10AI1/10AI2 9BI OUTPUT 10BO1/10BO2 L L L L HL H LL H H H INPUTS INPUT/OUTPUT 5A/6A OUTPUT 7BO1/7BO2 EN2 5BI/6BI 5A/6A (OPEN DRAIN) OUTPUT 7BO1/7BO2 H L L H† H HL‡ L H HH H L HL‡ L L HH H L LH H L L L‡ H INPUT 11BI INPUT/OUTPUT 11A (OPEN DRAIN) OUTPUT 11BO L H L L L‡ H H L H H = High voltage level L = Low voltage level † The enable on 7BO1/7BO2 includes a delay that prevents a transient condition (where 5BI/6BI goes from low to high, and the low to high on 5A/6A lags up to 100 ns) from causing a low glitch on the 7BO1/7BO2 outputs. ‡ Open-drain input/output terminal is driven to a logic-low state by an external driver. |
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