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ZL50030 Arkusz danych(PDF) 3 Page - Zarlink Semiconductor Inc |
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ZL50030 Arkusz danych(HTML) 3 Page - Zarlink Semiconductor Inc |
3 / 73 page ZL50030 Data Sheet 3 Zarlink Semiconductor Inc. Changes Summary The following table captures the changes from the March 2004 issue. Page Item Change 27, 47 Section 17.2 and Table 20 Added description clarifying that the MTIE reset must be set when the device is in the slave mode. 49 Table 21 Added MRST (bit 10) in Mode Selection table. 29, 30 Section 17.7 and Section 18.1 Deleted the intrinsic jitter descriptions in Section 17.7 and Section18.1, and replaced them with Table "AC Electrical Characteristics - Output Clock Jitter Generation (Unfiltered). 57 “AC Electrical Characteristics† - Output Frame Pulse and Output Clock Timing“ The parameter Delta, ∆, is replaced by actual numbers in all tables. 56 “AC Electrical Characteristics† - Input Frame Pulse and Input Clock Timing“ The Phase Correction, φ, is replaced by actual numbers. 65, 67 “AC Electrical Characteristics† - Backplane Serial Streams with Data Rate of 8 Mbps“, “AC Electrical Characteristics† - Backplane Serial Streams with Data Rate of 16 Mbps“ and “AC Electrical Characteristics† - Local Serial Stream Input Timing“ Input data sampling timings were updated for clarity purposes. |
Podobny numer części - ZL50030_06 |
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Podobny opis - ZL50030_06 |
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