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ADSP-BF561SKBCZ600 Arkusz danych(PDF) 1 Page - Analog Devices |
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ADSP-BF561SKBCZ600 Arkusz danych(HTML) 1 Page - Analog Devices |
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1 / 60 page  a Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Blackfin® Embedded Symmetric Multiprocessor ADSP-BF561 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved. FEATURES Dual symmetric 600 MHz high performance Blackfin cores 328K bytes of on-chip memory (see memory information on Page 4) Each Blackfin core includes: Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of program- ming and compiler-friendly support Advanced debug, trace, and performance monitoring 0.8 V to 1.35 V core V DD with on-chip voltage regulator 3.3 V and 2.5 V compliant I/O 256-ball mini-BGA and 297-ball PBGA package options PERIPHERALS Two parallel input/output peripheral interface units support- ing ITU-R 656 video and glueless interface to analog front end ADCs Two dual channel, full duplex synchronous serial ports sup- porting eight stereo I 2S channels Dual 16-channel DMA controllers and one internal memory DMA controller 12 general-purpose 32-bit timers/counters, with PWM capability SPI®-compatible port UART with support for IrDA® Dual watchdog timers 48 programmable flags On-chip phase-locked loop capable of 0.5 × to 64× frequency multiplication Figure 1. Functional Block Diagram VOLTAGE REGULATOR IRQ CONTROL/ WATCHDOG TIMER EXTERNAL PORT FLASH/SDRAM CONTROL 32 16 32 16 BOOT ROM PAB EAB DAB DAB PPI0 PPI1 JTAG TEST EMULATION GPIO SPI UART IrDA SPORT0 TIMERS SPORT1 IMDMA CONTROLLER L1 INSTRUCTION MEMORY L1 DATA MEMORY MMU B L2 SRAM 128K BYTES CORE SYSTEM/BUS INTERFACE L1 INSTRUCTION MEMORY L1 DATA MEMORY MMU B DEB DMA CONTROLLER1 DMA CONTROLLER2 IRQ CONTROL/ WATCHDOG TIMER |
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