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SN74ABT18502 Arkusz danych(PDF) 6 Page - Texas Instruments

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Numer części SN74ABT18502
Szczegółowy opis  SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER
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Producent  TI [Texas Instruments]
Strona internetowa  http://www.ti.com
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SN74ABT18502 Arkusz danych(HTML) 6 Page - Texas Instruments

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SN74ABT18502
SCAN TEST DEVICE
WITH 18-BIT REGISTERED BUS TRANSCEIVER
SCBS753 – FEBRUARY 2002
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
state diagram description
The TAP controller is a synchronous finite state machine that provides test control signals throughout the device.
The state diagram is shown in Figure 1 and is in accordance with IEEE Std 1149.1-1990. The TAP controller
proceeds through its states based on the level of TMS at the rising edge of TCK.
As illustrated, the TAP controller consists of sixteen states. There are six stable states (indicated by a looping
arrow in the state diagram) and ten unstable states. A stable state is defined as a state the TAP controller can
retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths though the state diagram: one to access and control the selected DR and one to
access and control the IR. Only one register can be accessed at a time.
Test-Logic-Reset
The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The IR is reset to an opcode that
selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain DRs may also be reset
to their power-up values.
The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. TMS has an internal pullup resistor that forces it high if left unconnected
or if a board defect causes it to be open circuited.
For the SN74ABT18502, the IR is reset to the binary value 10000001, which selects the IDCODE instruction.
Each bit in the BSR is reset to logic 0 except bits 83–80, which are reset to logic 1. The BCR is reset to the binary
value 000000000000000000010, which selects the PSA test operation with no input masking.
Run-Test/Idle
The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test/Idle state can also be entered following DR or IR scans. Run-Test/Idle is provided as
a stable state in which the test logic may be actively running a test or can be idle.
The test operations selected by the BCR are performed while the TAP controller is in the Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states are provided to allow the selection of either DR scan
or IR scan.
Capture-DR
When a DR scan is selected, the TAP controller must pass through the Capture-DR state. In the Capture-DR
state, the selected DR can capture a data value as specified by the current instruction. Such capture operations
occur on the rising edge of TCK upon which the TAP controller exits the Capture-DR state.
Shift-DR
Upon entry to the Shift-DR state, the DR is placed in the scan path between TDI and TDO and, on the first falling
edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present
in the least significant bit (LSB) of the selected DR.
While in the stable Shift-DR state, data is serially shifted through the selected DR on each TCK cycle. The first
shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during the
TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). The
last shift occurs on the rising edge of TCK upon which the TAP controller exits the Shift-DR state.


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