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TS924AIN Arkusz danych(PDF) 4 Page - STMicroelectronics |
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TS924AIN Arkusz danych(HTML) 4 Page - STMicroelectronics |
4 / 14 page Electrical Characteristics TS924 4/14 2 Electrical Characteristics Table 3. VCC = +3V, VDD = 0V, Vicm = VCC/2, Tamb = 25°C, RL connected to VCC/2 (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit Vio Input Offset Voltage - TS924 TS924A Tmin. ≤ Tamb ≤ Tmax. - TS924 TS924A 3 0.9 5 1.8 mV DVio Input Offset Voltage Drift 2 µV/°C Iio Input Offset Current Vout = Vcc/2 1 30 nA Iib Input Bias Current Vout = Vcc/2 15 100 nA VOH High Level Output Voltage RL= 100k RL = 600Ω RL = 32Ω 2.90 2.87 2.63 V VOL Low Level Output Voltage RL= 10k RL = 600Ω RL = 32Ω 180 50 100 mV Avd Large Signal Voltage Gain (Vout = 2Vpk-pk) RL= 10k RL = 600Ω RL = 32Ω 200 35 16 V/mV Icc Total Supply Current no load, Vout = Vcc/2 4.5 7 mA GBP Gain Bandwidth Product RL = 600Ω 4 MHz CMR Common Mode Rejection Ratio 60 80 dB SVR Supply Voltage Rejection Ratio - Vcc = 2.7 to 3.3V 60 85 dB Io Output Short Circuit Current 50 80 mA SR Slew Rate 0.7 1.3 V/ µs φm Phase Margin at Unit Gain - RL = 600Ω, CL =100pF 68 Degrees Gm Gain Margin - RL = 600Ω, CL =100pF 12 dB en Equivalent Input Noise Voltage - f = 1kHz 9 THD Total Harmonic Distortion Vout = 2Vpk-pk, F = 1kHz, Av = 1, RL =600Ω 0.005 % Cs Channel Separation 120 dB nV Hz ------------ |
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