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MC10E197 Arkusz danych(PDF) 5 Page - ON Semiconductor

Numer części MC10E197
Szczegółowy opis  5V ECL Data Separator
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Producent  ONSEMI [ON Semiconductor]
Strona internetowa  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC10E197 Arkusz danych(HTML) 5 Page - ON Semiconductor

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MC10E197
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5
APPLICATIONS INFORMATION
General Operation
Operation
The E197 is a phase-locked loop circuit consisting of an
internal VCO, a Data Phase detector with associated
acquisition circuitry, and a Phase/Frequency detector
(Figure 1). In addition, an enable pin(ENVCO) is provided to
disable the internal VCO and enable the external VCO input.
Hence, the user has the option of supplying the VCO signal.
The E197 contains two phase detectors: a data phase
detector for synchronizing to the non-periodic pulses in the
read data stream during the data read mode of operation, and
a phase/ frequency detector for frequency (and phase) locking
to an external reference clock during the “idle” mode of
operation. The read enable (RDEN) pin muxes between these
two detectors.
Data Read Mode
The data pins (RAWD) are enabled when the RDEN pin is
placed at a logic high level, thus enabling the Data Phase
detector (Figure1) and initiating the data read mode. In this
mode, the loop is servoed by the timing information taken from
the positive edges of the input data pulses. This phase detector
samples positive edges from the RAWD signal and generates
both a pump up and pump down pulse from any edge of the
input data pulse. The leading edge of the pump up pulse is time
modulated by the leading edge of the data signal, whereas the
rising edge of the pump up pulse is generated synchronous to
the VCO clock. The falling edge of the pump down pulse is
synchronous to the falling edge of the VCO clock and the rising
edge of the pump down signal is synchronous to the rising edge
of the VCO clock. Since both edges of the VCO are used the
internal clock a duty cycle of 50%. This pulse width
modulation technique is used to generate the servoing signal
which drives the VCO. The pump down signal is a reference
pulse which is included to provide an evenly balanced
differential system, thereby allowing the synthesis of a VCO
input control signal after appropriate signal processing by the
loop filter.
By using suitable external filter circuitry, a control signal for
input into the VCO can be generated by inverting the pump
down signal, summing the inverted signal with the pump up
signal and averaging the result. The polarity of this control
signal is defined as zero when the data edges lead the clock by
a half clock cycle. If the data edges are advanced with respect
to the zero polarity data/VCO edge relationship, the control
signal is defined to have a negative polarity; whereas if the
VCO is advanced with respect to the zero polarity data/VCO
edge relationship, the control signal is defined to have a
positive polarity. If there is no data edge present at the RAWD
input, the corresponding pump up and pump down outputs are
not generated and the resulting control output is zero.
Acquisition Circuitry
The acquisition circuitry is provided to assist the data phase
detector in phase locking to the sync field that precedes the
data. For the case in which lock-up is attempted when the data
edges are coincident with the VCO edges, the pump down
signal may enter an indeterminate state for an unacceptably
long period due to the violation of internal set up and hold
times. After an initial pump down pulse, the circuit blocks
successive pump down pulses, and inserts extra pump up
pulses, during portions of the sync field that are known to
contain zeros. Thus, the data phase detector is forced to have
a nonzero output during the lock-up period, and the restoring
force ensures correction of the loop within an acceptable time.
Hence, this circuitry provides a quasi-deterministic pump
down output signal, under the condition of coincident data and
VCO edges, allowing lock-up to occur with excessive delays.
The ACQ line is provided to disable (disable = HIGH) the
acquisition circuit during the data portion of a sector block.
Typically, this circuit is enabled at the beginning of the sync
field by a one-shot timer to ensure a timely lock-up.
The TYPE line allows the choice between two sync field
preamble types; transitions interspersed with two zeros
between transitions. These types of sync fields are used with
the 1:7 and 2:7 coding schemes, respectively.
Idle Mode
In the absence of data or when the drive is writing to the disk,
PLL servoing is accomplished by pulling the read enable line
(RDEN) low and providing a reference clock via the REFCLK
pins. The condition whereby RDEN is low selects the
Phase/Frequency detector (Figure 1) and the 10E197 is said to
be operating in the “idle mode”. In order to function as a
frequency detector the input waveform must be periodic. The
pump up and pump down pulses from the Phase/Frequency
detector will have the same frequency, phase and pulse width
only when the two clocks that are being compared have their
positive edges aligned and are of the same frequency.
As with the data phase detector, by using suitable external
filter circuitry, a VCO input control signal can be generated by
inverting the pump down signal, summing the inverted signal
with the pump up signal and averaging the result. The polarity
of this control signal is defined as zero when all positive edges
of both clocks are coincident. For the case in which the
frequencies of the two clocks are the same but the clock edges
of the reference clock are slightly advanced with respect to the
VCO clock, the control clock is defined to have a positive
polarity. A control signal with negative polarity occurs when
the edges of the reference clock are delayed with respect to
those of the VCO. If the frequencies of the two clocks are
different, the clock with the most edges per unit time will
initiate the most pulses and the polarity of the detector will
reflect the frequency error. Thus, when the reference clock is
high in frequency than the VCO clock the polarity of the
control signal is positive; whereas a control signal with
negative polarity occurs when the frequency of the reference
clock is lower than the VCO clock.


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