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MV1403 Arkusz danych(PDF) 11 Page - Zarlink Semiconductor Inc |
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MV1403 Arkusz danych(HTML) 11 Page - Zarlink Semiconductor Inc |
11 / 18 page MV1403 10 PIN DESCRIPTIONS Symbol Pin No. Mode Pin name and description name DP48 HP44 (see note 1) VDD1 GLOBAL Digital supply voltage. 5V (Note 2) ER 2 2 RX Timeslot Zero Receiver (RXTSZ) Macrocell - Sync Word Error Output (ER). This flag goes high for one frame immediately after detection of a bad timeslot zero sync word, whilst the macrocell is in sync. Three consecutive errors of this type will put the receiver out of sync. The last ER pulse of this sequence will be longer than 256 periods if a valid sync word is detected during the pulse. MFQ1 3 3 RX Timeslot Zero Receiver (RXTSZ) Macrocell - Synchronisation Alarm Output (SA). This error flag goes high when the macrocell is out of sync and only changes state at the end of a sync frame timeslot zero. TX Timeslot Zero Transmitter (TXTSZ) Macrocell - Timeslot Zero Sync frame marker (TZS). This output is high during timeslot zero of sync frames and changes state at the beginning of timeslot one, bit 2 of every frame. MFQ2 4 4 RX Timeslot Zero Receiver (RXTSZ) Macrocell - Remote Alarm Indication Output (RAI) This is a persistence checked version of the Q3N output. When RXTSZ is in sync, this output goes high if the current and previous timeslot zero bit 3 of non-sync frames are both high. This output changes state at bit 1, timeslot 1 of non-sync frames. When the macrocell is out of sync this output is forced low in the non-sync frame following the last bad sync frame, and is held low until the macrocell comes back into sync. TX Timeslot Zero Transmitter (TXTSZ) Macrocell - Data Output (Q). The sync word and signalling data word appear here in 8 bit bursts during timeslot zero. Bit 1 appears immediately after the rising edges of CLK and FRS. This output is low during all timeslots except timeslot zero. DQ8 5 5 RX Timeslot Zero Receiver (RXTSZ) Macrocell - Data Outputs (Q8N-Q3N). These DQ7 6 6 outputs are extracted from bits 8-3 of timeslot zero during non-sync frames DQ6 7 7 respectively. These outputs change at the start of bit 1, timeslot 1 of non-sync DQ5 8 8 frames . DQ4 9 9 DQ3 10 10 TX Timeslot Zero Transmitter (TXTSZ) Macrocell Data Inputs (D8N-D3N). These data inputs are inserted into bits 8-3 of timeslot zero during non-sync frames respectively. This data must be set up prior to the rising edge of FRS. DQ1 11 11 RX Timeslot Zero Receiver (RXTSZ) Macrocell - Data Output (Q1 N). With CRC = 0, this output latches data from bit I, timeslot zero of non-sync frames. The output changes at the beginning of bit l, timeslot 1 of non-sync frames. With CRC=1, this output latches data from bit 1 of frame 15 of the CRC multiframe. TX1 Timeslot Zero Transmitter (TXTSZ) Macrocell - Data Input (D1). The data on this pin is inserted into the International spare bit (bit 1, timeslot zero of both sync and non-sync frames), and must be set up prior to the rising edge of . FRS. TX2 This pin is unused since the Dl input of the Timeslot Zero Transmitter is connected internally to the Q output of the CRC Generator. Q1S 12 12 RX Timeslot Zero Receiver (RXTSZ) Macrocell - Data Output (Q1S). With CRC = 0, this output latches data from bit 1, timeslot zero of sync frames. The output changes at the beginning of bit 1, timeslot 1 of sync frames. With CRC = 1, this output latches data from bit 1 of frame 13 of the CRC multiframe. V DD2 13 - GLOBAL Digital supply voltage. 5V (Note 2) GND1 14 13 GLOBAL Digital ground. 0V (Note 2) LIA 15 14 RX HDB3 Decoder (HDB3DC) Macrocell - Loss of Input Alarm Output (LIA). This alarm output goes high after 11 consecutive zeros have been detected on the HDB3 inputs. It is reset on detection of a mark (1) on either HDB3 input. |
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