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MV1403 Arkusz danych(PDF) 2 Page - Zarlink Semiconductor Inc

Numer części MV1403
Szczegółowy opis  PCM MACROCELL DEMONSTRATOR
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Producent  ZARLINK [Zarlink Semiconductor Inc]
Strona internetowa  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MV1403 Arkusz danych(HTML) 2 Page - Zarlink Semiconductor Inc

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MV1403
1
DS3046-2.1
MV1403
PCM MACROCELL DEMONSTRATOR
The MV1403 contains 8 PCM macrocells which can be
configured so as to perform the common channel signalling
and error detection functions for a 2.048 Mbit 30 channel PCM
transmission link, operating to the appropriate CCITT
recommendations. The MV1403 also allows access to all the
macrocells individually and is implemented in GPS CMOS
technology utilising the CLA60000 series gate array, offering
high performance, low power and fast turn-round. The
following macrocells are included in the MV1403.
Timeslot Zero Transmitter - TXTSZ
Timeslot Sixteen Transmitter - TXTS16
Cyclic Redundancy Check Generator - CRCGEN
High Density Bipolar (HDB) 3 Encoder - HDB3EC
Timeslot Zero Receiver - RXTSZ
Timeslot Sixteen Receiver - RXTS16
Cyclic Redundancy Checker - CRCCHK
High Density Bipolar (HDB) 3 Decoder - HDB3DC
With the MV1403 set up to combine the internal
macrocells, two demonstration modes are available, referred
to as Transmit and Receive demonstration modes.
In Transmit demonstration mode, timeslot zero sync word
(including user data bits and optional CRC check bits), timeslot
sixteen data and 30 voice channels are combined and
transmitted as pseudo-ternary HDB3 encoded outputs. The
Transmit demonstration mode can also be set to generate
CRC
multiframe
data
in
accordance
with
CCITT
Recommendation G. 704.
In Receive demonstration mode, the pseudo-ternary HDB3
inputs are decoded back to NRZ form and frame
synchronisation is achieved by detection of the Frame
Alignment signal in the incoming data stream. This permits
extraction of user data bits, timeslot sixteen data and voice
channel data. An optional CRC mode generates CRC
multiframe alignment and a cyclic redundancy check is carried
out on the incoming data. In addition receive demonstration
mode generates appropriate alarms for loss of input, double
violation on the HDB3 inputs, loss of frame or CRC multiframe
alignment, detection of erroneous frame alignment word,
remote alarm received from the transmitter, and detection of a
CRC error in either submultiframe 1 or 2.
FEATURES
s Single + 5V Supply
s All Inputs and Outputs TTL Compatible
s Selectable as PCM Transmitter or Receiver
s Allows Access to all 8 Macrocells Individually
s HDB3 Encoding and Decoding to CCITT
Recommendation G. 703
s Transmitted Frame Structure to CCITT
Recommendation G. 704
s Receiver Frame Synchronisation to CCITT
s Recommendation G. 732
s Selectable CRC Mode
s CRC Generation and Checking to CCITT
Recommendation G. 704
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48
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VDD1
ER
MFQ1
MFQ2
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ1
Q1S
VDD2
GND1
LIA
MFQ3
MFQ4
MFQ5
FRS13RZ
MFD1
MFD2
MFD3
MFD4
VDD3
GND4
CCR
CK8
TZSRZ
TSZRZ
MFQ9
FRS13
FRS15
MFQ8
MFQ7
MFQ6
RST
GND3
MFD6
TZS
FRS
MFD5
CRC
P
STM
CLK
MODE
DEMO
GND2
MV
1403
DP
DP48
MV 1403
HP
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
1
44
43
42
41
40
DQ7
DQ8
MFQ2
MFQ1
ER
GND2
CCR
CK8
TZSRZ
TSZRZ
MFQ9
FRS13RZ
MFD1
MFD2
MFD3
MFD4
VDD
DEMO
MODE
CLK
STM
P
HP44
PIN 1 IDENT
Figure 1: Pin connections - top view
NOTE:
MFD is multi-function input,
MFQ is multi-function output
ADVANCE INFORMATION


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