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ADSP-21367BBPZ-2A Arkusz danych(PDF) 1 Page - Analog Devices

Numer części ADSP-21367BBPZ-2A
Szczegółowy opis  SHARC Processors
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Strona internetowa  http://www.analog.com
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SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SHARC® Processors
ADSP-21367/ADSP-21368/ADSP-21369
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—2M bit of on-chip SRAM and 6M bit of on-
chip mask programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21367/ADSP-21368/ADSP-21369 are available
with a 333 MHz core instruction rate with unique audiocen-
tric peripherals such as the digital audio interface, S/PDIF
transceiver, serial ports, 8-channel asynchronous sample
rate converter, precision clock generators, and more. For
complete ordering information, see Ordering Guide on
Page 56.
Figure 1. Functional Block Diagram
SPI PORT (2)
TIMERS (3)
TWO WIRE
INTERFACE
UART (2)
DIGITAL PERIPHERAL INTERFACE
GPIO FLAGS/
IRQ/TIMEXP
4
SERIAL PORTS (8)
INPUT DATA PORT/
PDAP
SPDIF (Rx/Tx)
DIGITAL AUDIO INTERFACE
IOD(32)
ADDR
DATA
IOA(24)
4 BLOCK OF
ON-CHIP MEMORY
PM DATA BUS
DM DATA BUS
32
PM ADDRESS BUS
DM ADDRESS BUS
64
PX REGISTER
PROCESSING
ELEMENT
(PEY)
TIMER
INSTRUCTION
CACHE
32
× 48-BIT
DAG1
8
× 4 × 32
PROGRAM
SEQUENCER
DMA
CONTROLLER
34 CHANNELS
S
MEMORY-TO-
MEMORY DMA (2)
IOP REGISTER (MEMORY MAPPED)
CONTROL, STATUS, & DATA BUFFERS
JTAG TEST & EMULATION
I/O PROCESSOR
DAI PINS
DPI PINS
64
32
14
20
SRC (8 CHANNELS)
PRECISION CLOCK
GENERATORS (4)
24
18
SDRAM
CONTROLLER
ADDRESS
CONTROL
3
7
ASYNCHRONOUS
MEMORY INTERFACE
SHARED MEMORY
INTERFACE
8
EXTERNAL PORT
PWM
32
DATA
FLAGS4-15
CORE PROCESSOR
DAG2
8
× 4 × 32
PROCESSING
ELEMENT
(PEX)
2M BIT RAM
6M BIT ROM


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