 |
Zakładka z wyszukiwarką danych komponentów |
|
|
Zakładka z wyszukiwarką danych komponentów |
|
ADSP-21369KSZ-1A Arkusz danych(PDF) 9 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
ADSP-21369KSZ-1A Arkusz danych(HTML) 9 Page - Analog Devices |
|
|
9 / 56 page  ADSP-21367/ADSP-21368/ADSP-21369 Rev. A | Page 9 of 56 | August 2006 In conjunction with the general-purpose timer functions, auto- baud detection is supported. Timers The ADSP-21367/ADSP-21368/ADSP-21369 have a total of four timers: a core timer that can generate periodic software interrupts and three general-purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes: • Pulse waveform generation mode • Pulse width count/capture mode • External event watchdog mode The core timer can be configured to use FLAG3 as a timer expired signal, and each general purpose timer has one bidirec- tional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A sin- gle control and status register enables or disables all three general-purpose timers independently. Two-Wire Interface Port (TWI) The TWI is a bidirectional 2-wire, serial bus used to move 8-bit data while maintaining compliance with the I2C bus protocol. The TWI master incorporates the following features: • Simultaneous master and slave operation on multiple device systems with support for multimaster data arbitration • Digital filtering and timed event processing • 7-bit and 10-bit addressing • 100K bits/s and 400K bits/s data rates • Low interrupt rate Pulse-Width Modulation The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM wave- forms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in non- paired mode (applicable to a single group of four PWM waveforms). The entire PWM module has four groups of four PWM outputs each. Therefore, this module generates 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs. The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the midpoint of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to pro- duce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. ROM-Based Security The ADSP-21367/ADSP-21368/ADSP-21369 have a ROM secu- rity feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. When using this feature, the pro- cessor does not boot-load any external code, executing exclusively from internal SRAM/ROM. Additionally, the pro- cessor is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or test access port will be assigned to each customer. The device will ignore a wrong key. Emulation features and external boot modes are only available after the correct key is scanned. SYSTEM DESIGN The following sections provide an introduction to system design options and power supply issues. Program Booting The internal memory of the processors can be booted up at sys- tem power-up from an 8-bit EPROM via the external port, an SPI master or slave, or an internal boot. Booting is determined by the boot configuration (BOOT_CFG1–0) pins (see Table 7 on Page 15). Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM. Power Supplies The processors have separate power supply connections for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.3 V requirement for the 333 MHz device and 1.2 V for the 266 MHz device. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply. Note that the analog supply pin (AVDD) powers the processor’s internal clock generator PLL. To produce a stable clock, it is rec- ommended that PCB designs use an external filter circuit for the AVDD pin. Place the filter components as close as possible to the AVDD/AVSS pins. For an example circuit, see Figure 2. (A recom- mended ferrite chip is the muRata BLM18AG102SN1D). To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for VDDINT and GND. Use wide traces to connect the bypass capacitors to the analog power (AVDD) and ground (AVSS) pins. Note that the AVDD and AVSS pins specified in Figure 2 are inputs to the processor and not the analog ground plane on the board—the AVSS pin should connect directly to dig- ital ground (GND) at the chip. |
Podobny numer części - ADSP-21369KSZ-1A |
|
Podobny opis - ADSP-21369KSZ-1A |
|
|
Link URL |
| Polityka prywatności |
| ALLDATASHEET.PL |
| Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Polish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
