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MC74VHCT50AMG Arkusz danych(PDF) 1 Page - ON Semiconductor |
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1 / 7 page © Semiconductor Components Industries, LLC, 2007 January, 2007− Rev. 6 1 Publication Order Number: MC74VHCT50A/D MC74VHCT50A Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs The MC74VHCT50A is a hex noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffered output which provides high noise immunity and stable output. The device input is compatible with TTL−type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic−level translator from 3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high−voltage power supply. The MC74VHCT50A input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHCT50A to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc. • High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V • Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C • TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V • CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load • Power Down Protection Provided on Inputs and Outputs • Pb−Free Packages are Available LOGIC DIAGRAM Y1 A1 A2 A3 A4 A5 A6 Y2 Y3 Y4 Y5 Y6 1 3 5 9 11 13 2 4 6 8 10 12 Y = A A1 Y1 1 A2 Y2 1 A3 Y3 1 A4 Y4 1 A5 Y5 1 A6 Y6 1 LOGIC SYMBOL 14−LEAD SOIC D SUFFIX CASE 751A 14−LEAD TSSOP DT SUFFIX CASE 948G PIN CONNECTION AND MARKING DIAGRAM (Top View) 13 14 12 11 10 9 8 2 1 34567 VCC A6 Y6 A5 Y5 A4 Y4 A1 Y1 A2 Y2 A3 Y3 GND 14−LEAD SOIC EIAJ M SUFFIX CASE 965 FUNCTION TABLE L H A Input Y Output L H For detailed package marking information, see the Marking Diagram section on page 4 of this data sheet. http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ORDERING INFORMATION |
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