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MC100LVEL59DWR2G Arkusz danych(PDF) 1 Page - ON Semiconductor |
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1 / 6 page © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 4 1 Publication Order Number: MC100LVEL59/D MC100LVEL59 3.3V ECL Triple 2:1 Multiplexer Description The MC100LVEL59 is a 3.3 V triple 2:1 multiplexer with differential outputs. The output data of the multiplexers can be controlled individually via the select inputs or as a group via the common select input. The flexible selection scheme makes the device useful for both data path and random logic applications. Features • Individual or Common Select Controls • 500 ps Typical Propagation Delays • ESD Protection: >2 kV HBM • The 100 Series Contains Temperature Compensation • PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V • Internal Input Pulldown Resistors • Q Output will Default LOW with Inputs Open or at VEE • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity; Pb Pkg Level 1 Pb−Free Pkg Level 3 For Additional Information, see Application Note AND8003/D • Flammability Rating: UL 94 V−O @ 0.125 in, Oxygen Index 28 to 34 • Transistor Count = 182 devices • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ORDERING INFORMATION *For additional marking information, refer to Application Note AND8002/D. MARKING DIAGRAM* A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G= Pb−Free Package SO−20 WB DW SUFFIX CASE 751D 20 1 100LVEL59 AWLYYWWG |
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