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MC14042BDR2G Arkusz danych(PDF) 1 Page - ON Semiconductor

Numer części MC14042BDR2G
Szczegółowy opis  Quad Transparent Latch
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Producent  ONSEMI [ON Semiconductor]
Strona internetowa  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 6
1
Publication Order Number:
MC14042B/D
MC14042B
Quad Transparent Latch
The MC14042B Quad Transparent Latch is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each latch has a separate data input, but all four
latches share a common clock. The clock polarity (high or low) used to
strobe data through the latches can be reversed using the polarity
input. Information present at the data input is transferred to outputs Q
and Q during the clock level which is determined by the polarity input.
When the polarity input is in the logic “0” state, data is transferred
during the low clock level, and when the polarity input is in the logic
“1” state the transfer occurs during the high clock level.
Features
Buffered Data Inputs
Common Clock
Clock Polarity Control
Q and Q Outputs
Double Diode Input Protection
Supply Voltage Range = 3.0 Vdc to 1 8 Vdc
Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
−0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
−0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
MC14042BCP
AWLYYWWG
SOIC−16
D SUFFIX
CASE 751B
14042BG
AWLYWW
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
G
= Pb−Free Indicator
SOEIAJ−16
F SUFFIX
CASE 966
MC14042B
ALYWG
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
16
1
1
16
1
16


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