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MC14046BFELG Arkusz danych(PDF) 1 Page - ON Semiconductor

Numer części MC14046BFELG
Szczegółowy opis  Phase Locked Loop
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Producent  ONSEMI [ON Semiconductor]
Strona internetowa  http://www.onsemi.com
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MC14046BFELG Arkusz danych(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 10
1
Publication Order Number:
MC14046B/D
MC14046B
Phase Locked Loop
The MC14046B phase locked loop contains two phase comparators,
a voltage−controlled oscillator (VCO), source follower, and zener
diode. The comparators have two common signal inputs, PCAin and
PCBin. Input PCAin can be used directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to small voltage
signals. The self−bias circuit adjusts small voltage signals in the linear
region of the amplifier. Phase comparator 1 (an exclusive OR gate)
provides a digital error signal PC1out, and maintains 90° phase shift at
the center frequency between PCAin and PCBin signals (both at 50%
duty cycle). Phase comparator 2 (with leading edge sensing logic)
provides digital error signals, PC2out and LD, and maintains a 0°
phase shift between PCAin and PCBin signals (duty cycle is
immaterial). The linear VCO produces an output signal VCOout
whose frequency is determined by the voltage of input VCOin and the
capacitor and resistors connected to pins C1A, C1B, R1, and R2. The
source−follower output SFout with an external resistor is used where
the VCOin signal is needed but no loading can be tolerated. The inhibit
input Inh, when high, disables the VCO and source follower to
minimize standby power consumption. The zener diode can be used to
assist in power supply regulation.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
t one decodi ng, dat a synchroni zat i o n and condi t i oni ng,
voltage−to−frequency conversion and motor speed control.
Features
Buffered Outputs Compatible with MHTL and Low−Power TTL
Diode Protection on All Inputs
Supply Voltage Range = 3.0 to 18 V
Pin−for−Pin Replacement for CD4046B
Phase Comparator 1 is an Exclusive OR Gate and is Duty Cycle Limited
Phase Comparator 2 Switches on Rising Edges and is not Duty Cycle
Limited
Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
−0.5 to +18.0
V
Vin
Input Voltage Range (All Inputs)
−0.5 to VDD + 0.5
V
Iin
DC Input Current, per Pin
±10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Operating Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
MC14046BCP
AWLYYWWG
SOIC−16
DW SUFFIX
CASE 751G
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
G
= Pb−Free Indicator
SOEIAJ−16
F SUFFIX
CASE 966
MC14046B
ALYWG
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
16
1
1
16
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
14046BG
AWLYYWW
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid ap-
plications of any voltage higher than maximum rated
voltages to this high−impedance circuit. For proper op-
eration, Vin and Vout should be constrained to the range
VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused out-
puts must be left open.
16
1


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