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MC14046BFELG Arkusz danych(PDF) 2 Page - ON Semiconductor |
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MC14046BFELG Arkusz danych(HTML) 2 Page - ON Semiconductor |
2 / 8 page MC14046B http://onsemi.com 2 PIN ASSIGNMENT 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 R2 PC2out PCAin ZENER VDD VCOin SFout R1 VCOout PCBin PC1out LD VSS C1B C1A INH BLOCK DIAGRAM PCAin PCBin VCOin INH 14 3 9 5 VDD = PIN 16 VSS = PIN 8 2PC1out 13PC2out 1LD 4VCOout 11R1 12R2 6C1A 7C1B 10SFout 15ZENER VSS SELF BIAS CIRCUIT PHASE COMPARATOR 1 PHASE COMPARATOR 2 VOLTAGE CONTROLLED OSCILLATOR (VCO) SOURCE FOLLOWER ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol VDD Vdc − 55 _C 25 _C 125 _C Unit Min Max Min Typ Max Min Max Output Voltage “0” Level Vin = VDD or 0 “1” Level Vin = 0 or VDD VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc Input Voltage (Note 2) “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) (VO = 0.5 or 4.5 Vdc) “1” Level (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 Vdc VIH 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − Vdc Output Drive Current (VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) IOH 5.0 5.0 10 15 – 1.2 – 0.25 – 0.62 – 1.8 − − − − – 1.0 – 0.2 – 0.5 – 1.5 – 1.7 – 0.36 – 0.9 – 3.5 − − − − – 0.7 – 0.14 – 0.35 – 1.1 − − − − mAdc IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current Iin 15 − ± 0.1 − ±0.00001 ± 0.1 − ± 1.0 mAdc Input Capacitance Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) Inh = PCAin = VDD, Zener = VCOin = 0 V, PCBin = VDD or 0 V, Iout = 0 mA IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 − − − 150 300 600 mAdc Total Supply Current (Note 3) (Inh = “0”, fo = 10 kHz, CL = 50 pF, R1 = 1.0 M W, R2 = R RSF = ∞, and 50% Duty Cycle) IT 5.0 10 15 IT = (1.46 mA/kHz) f + IDD IT = (2.91 mA/kHz) f + IDD IT = (4.37 mA/kHz) f + IDD mAdc 2. Noise immunity specified for worst−case input combination. Noise Margin for both “1” and “0” level = 1.0 Vdc min @ VDD = 5.0 Vdc 2.0 Vdc min @ VDD = 10 Vdc 2.5 Vdc min @ VDD = 15 Vdc 3. To Calculate Total Current in General: IT [ 2.2 x VDD + 1 x 10−3 (CL + 9) VDD f + VCOin – 1.65 + VDD − 1.35 3/4 R1 R2 VCOin – 1.65 3/4 + 1.6 x where: IT in mA, CL in pF, VCOin, VDD in Vdc, f in kHz, and R1, R2, RSF in MW, CL on VCOout. RSF 1 x 10−1 VDD2 100% Duty Cycle of PCAin 100 + IQ |
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