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ADCMP341YRJZ-REEL7 Arkusz danych(PDF) 10 Page - Analog Devices |
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ADCMP341YRJZ-REEL7 Arkusz danych(HTML) 10 Page - Analog Devices |
10 / 12 page ADCMP341/ADCMP343 Rev. 0 | Page 10 of 12 APPLICATION INFORMATION The ADCMP341/ADCMP343 are dual, low power comparators with a built-in 400 mV reference that operates from 1.7 V to 5.5 V. The comparators are 0.275% accurate with fully programmable hysteresis, implemented using a new technique of a three-resistor string on the input. These open-drain outputs are capable of sinking up to 40 mA. COMPARATORS AND INTERNAL REFERENCE Each of the comparators has one input available externally; the other comparator inputs are connected internally to the 400 mV reference. The ADCMP341 has two noninverting comparators and the ADCMP343 has two inverting comparators. There are two input pins available to each comparator. However, these two input pins (±INx_U, ±INx_L) connect to the same input leg of the comparator via a muxing system. This is to provide fully programmable rising and falling trip points. The output of the comparator determines which pin is connected to the input of the same comparator. Using Figure 28 as an example, when OUTA is high, +INA_U is connected to the comparator input. When the input voltage drops and passes below the 400 mV reference, the output goes low. This in turn disconnects +INA_U from the comparator and connects +INA_L. This leg of the string is at a lower voltage and thus instantaneously the effect of hysteresis is applied. Therefore, using a resistor string on the input as shown in Figure 28, the voltages for the rising and falling trip points can be programmed by selecting the appropriate resistors in the string. POWER SUPPLY The ADCMP341/ADCMP343 are designed to operate from 1.7 V to 5.5 V. A 0.1 μF decoupling capacitor is recommended between VDD and GND. INPUTS The comparator inputs are limited to the maximum VDD voltage range. The voltage on these inputs can be above VDD but never above the maximum allowed VDD voltage. OUTPUTS The open-drain comparator outputs are limited to the maximum specified VDD voltage range, regardless of the VDD voltage. These outputs are capable of sinking up to 40 mA. Outputs can be tied together to provide a common output signal. PROGRAMMING HYSTERESIS When choosing the resistor values, the input bias current must be considered as a potential source of error. Begin by choosing a resistor value for R3, which takes into account the acceptable error introduced by the maximum specified input bias current. To reduce this error, the current flowing through the Resistor R3 should be considerably greater than the input bias current. BIAS R3 I I >> R3 is therefore 3 3 R REF I V R = Now R2 can be calculated from the following: ( ) FALLING FALLING RISING V V V R R − = 3 2 R1 can then be calculated using the following equation: 2 1 3 1 R V V R R REF RISING − ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ − × = where: VREF is the specified on chip reference. IBIAS is the maximum specified input bias current. R1, R2, and R3 are the three resistors as shown in Figure 28. IR3 is the current flowing through R3. VFALLING is the desired falling trip voltage and lower of the two. VRISING is the desired rising trip voltage and higher of the two. +INA_U OUTA VDD 400mV ADCMP341 +INA_L VINA R1 R2 R3 Figure 28. Programming Hysteresis Example LAYOUT RECOMMENDATIONS Correct layout is very important to increase noise immunity. Long tracks from the input resistors to the device can lead to noise being coupled onto the inputs. To avoid this, it is best to place the input resistors as close as possible to the device. It is also recommended that a GND plane is used under this layout. The combination of small hysteresis and the use of a large R3 resistor further increases susceptibility to noise. In this case, a decoupling capacitor (CA, CB) may be required on the ±INx_U node to help reduce any noise. A recommended layout example can be seen in Figure 29. C1 CA CB U1 GND VDD OUTA INA R1A R2A R3A OUTB INB R1B R2B R3B Figure 29. Recommended Layout Example |
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