ADCMP572/ADCMP573

Rev. 0 | Page 6 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

5

6

7

8

ADCMP572

ADCMP573

TOP VIEW

(Not to Scale)

1

PIN1

2

3

4

16

15

14

13

12

Q

11

Q

10

9

Figure 2. ADCMP572/ADCMP573 Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

Noninverting Analog Input.

3

Inverting Analog Input.

4

5, 16

Positive Supply Voltage for Input Stage.

6

LE

Latch Enable Input Pin, Inverting Side.

In compare mode (LE = low), the output tracks changes at the input of the comparator.

In latch mode (LE = high), the output reflects the input state just prior to the comparator’s being

placed into latch mode. LE must be driven in complement with LE.

7

LE

Latch Enable Input Pin, Noninverting Side.

In compare mode (LE = high), the output tracks changes at the input of the comparator.

In latch mode (LE = low), the output reflects the input state just prior to the comparator’s being

placed into latch mode. LE must be driven in compliment with LE.

8

Termination Return Pin for the LE/LE Input Pins.

For the ADCMP572 (CML output stage), this pin is internally connected to and also should be

termination potential.

9, 12

Positive Supply Voltage for the CML/RSPECL Output Stage.

13, 15

GND

Ground.

10

Q

LE/LE descriptions (Pins 6 and 7) for more information.

11

Q

the LE/LE descriptions (Pins 6 and 7) for more information.

14

HYS

Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect to GND with a

suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 7 for proper sizing of

Isolated

Heat sink

N/C

The metallic back surface of the package is not electrically connected to any part of the circuit, and it

can be left floating for best electrical isolation between the package handle and the substrate of the

die. However, it can be soldered to the application board if improved thermal and/or mechanical

stability is desired.