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ADT7302ARTZ-500RL7 Arkusz danych(PDF) 4 Page - Analog Devices |
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ADT7302ARTZ-500RL7 Arkusz danych(HTML) 4 Page - Analog Devices |
4 / 16 page ADT7302 Rev. 0 | Page 4 of 16 TIMING CHARACTERISTICS Guaranteed by design and characterization, not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. TA = TMIN to TMAX, VDD = 2.7 V to 5.25 V, unless otherwise noted. Table 2. Parameter1 Limit Unit Comments t1 5 ns min CS to SCLK Setup Time t2 25 ns min SCLK High Pulse Width t3 25 ns min SCLK Low Pulse Width t42 35 ns max Data Access Time After SCLK Falling Edge t5 20 ns min Data Setup Time Prior to SCLK Rising Edge t6 5 ns min Data Hold Time After SCLK Rising Edge t7 5 ns min CS to SCLK Hold Time t82 40 ns max CS to DOUT High Impedance 1 See Figure 14 for the SPI timing diagram. 2 Measured with the load circuit of Figure 2. 1.6V 200 μA 200 μAI OH IOL TO OUTPUT PIN CL 50pF Figure 2. Load Circuit for Data Access Time and Bus Relinquish Time |
Podobny numer części - ADT7302ARTZ-500RL7 |
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Podobny opis - ADT7302ARTZ-500RL7 |
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