REV. A

AD8350

–10–

87

6

5

12

34

AD8350

–

ENBL (5V)

0.1 F

Figure 8. Gain Reduction Using Shunt Resistor

87

6

5

12

34

AD8350

–

ENBL

(5V)

(5V TO 10V)

0.1 F

Figure 9. Dynamic Gain Reduction

Figure 8 shows a typical implementation of the shunt divider

concept. The reduced input impedance that results from the

parallel combination of the shunt resistor and the input impedance

of the AD8350 adds attenuation to the input signal effectively

reducing the gain. For frequencies less than 100 MHz, the input

impedance of the AD8350 can be modeled as a real 200

Ω resis-

tance (differential). Assuming the frequency is low enough to

ignore the shunt reactance of the input, and high enough such

that the reactance of moderately sized ac-coupling capacitors

can be considered negligible, the insertion loss, IL, due to the

shunt divider can be expressed as:

IL dB

Log

R

RR

RR

RR

R

RR

RR

RR

R

gl

nded

IN

IN

S

IN

SHUNT

IN

SHUNT

S

IN

SHUNT

IN

SHUNT

IN

SHUNT

IN

()

()

()

=×

+

+

























=

×

+

=−

20

100

10

where

and

Ω sin e e

(3)

The insertion loss and the resultant power gain for multiple

shunt resistor values is summarized in Table I. The source

resistance and input impedance need careful attention when

using Equation 1. The reactance of the input impedance of the

AD8350 and the ac-coupling capacitors need to be considered

before assuming they have negligible contribution. Figure 10

the AD8350-15 and AD8350-20.

Table I. Gain Adjustment Using Shunt Resistor,

Single-Ended

Power Gain–dB

IL–dB

AD8350-15

AD8350-20

50

6.02

8.98

13.98

100

3.52

11.48

16.48

200

1.94

13.06

18.06

300

1.34

13.66

18.66

400

1.02

13.98

18.98

20

0

18

16

14

12

10

8

6

4

2

0

100

200

300

400

500

600

700

800

AD8350-20

AD8350-15

Figure 10. Gain for Multiple Values of Shunt Resistance

for Circuit in Figure 8

The gain can be adjusted dynamically by employing external

feedback resistors as shown in Figure 9. The effective attenua-

tion is a result of the lowered input impedance as with the shunt

resistor method, yet there is no additional noise contribution at

the input of the device. It is necessary to use well-matched resistors

to minimize common-mode offset errors. Quality 1% tolerance

resistors should be used along with a symmetric board layout to

help guarantee balanced performance. The effective gain for mul-

tiple values of external feedback resistors is shown in Figure 11.