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SN74V225-10PAG Arkusz danych(PDF) 4 Page - Texas Instruments |
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SN74V225-10PAG Arkusz danych(HTML) 4 Page - Texas Instruments |
4 / 43 page SN74V215, SN74V225, SN74V235, SN74V245 512 × 18, 1024 × 18, 2048 × 18, 4096 × 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION D0–D17 1–16, 63, 64 I Data inputs. Data inputs for an 18-bit bus. EF/OR 54 O Memory-empty/valid-data-available flag. In the standard mode, the EF function is selected. EF indicates whether the FIFO memory is empty. In FWFT mode, the OR function is selected. OR indicates whether there is valid data available at the outputs. FF/IR 25 O Memory-full/space-available flag. In the standard mode, the FF function is selected. FF indicates whether the FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether there is space available for writing to the FIFO memory. FL 18 I Mode selection. In the single-device or width-expansion configuration, FL, together with WXI and RXI, determines if the mode is standard mode or first-word fall-through (FWFT) mode, as well as whether the PAE/PAF flags are synchronous or asynchronous (see Table 4). In the daisy-chain depth-expansion configuration, FL is grounded on the first device (first-load device) and set to high for all other devices in the daisy chain. GND 30, 35, 40, 46, 51, 55, 62 Ground LD 59 I Read/write control. When LD is low, data on the inputs D0–D11 is written to the offset and depth registers on the low-to-high transition of the WCLK, when WEN is low. When LD is low, data on the outputs Q0–Q11 is read from the offset and depth registers on the low-to-high transition of RCLK when REN is low. OE 58 I Output enable. When OE is low, the data output bus is active. If OE is high, the output data bus is in the high-impedance state. PAE 17 O Programable almost-empty flag. When PAE is low, the FIFO is almost empty, based on the offset programmed into the FIFO. The default offset at reset is 63 from empty for SN74V215, and 127 from empty for SN74V225, SN74V235, and SN74V245. PAF 23 O Programable almost-full flag. When PAF is low, the FIFO is almost full, based on the offset programmed into the FIFO. The default offset at reset is 63 from full for SN74V215, and 127 from full for SN74V225, SN74V235, and SN74V245. Q0–Q17 28, 29, 31, 32, 34, 36–39, 41, 42, 44, 45, 47, 48, 50, 52, 53 O Data outputs. Data outputs for an 18-bit bus. RCLK 61 I Read clock. When REN is low, data is read from the FIFO on a low-to-high transition of RCLK, if the FIFO is not empty. REN 60 I Read enable. When REN is low, data is read from the FIFO on every low-to-high transition of RCLK. When REN is high, the output register holds the previous data. Data is not read from the FIFO if EF is low. RS 57 I Reset. When RS is set low, internal read and write pointers are set to the first location of the RAM array, FF and PAF go high, and PAE and EF go low. A reset is required before an initial write after power up. RXI 24 I Read expansion. In the single-device or width-expansion configuration, RXI, together with FL and WXI, determines if the mode is standard mode or FWFT mode, as well as whether the PAE/PAF flags are synchronous or asynchronous (see Table 4). In the daisy-chain depth-expansion configuration, RXI is connected to RXO (read expansion out) of the previous device. RXO 27 O Last-location-read flag. In the depth-expansion configuration, a pulse is sent from RXO to RXI of the next device when the last location in the FIFO is read. VCC 22, 33, 43, 49, 56 Supply voltage. +3.3-V power-supply pins. WCLK 19 I Write clock. When WEN is low, data is written into the FIFO on a low-to-high transition of WCLK if the FIFO is not full. |
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